Texas Instruments CD4077BPWR, CD4077BM, CD4077BF3A, CD4077BF, CD4077BE Datasheet

[ /Title (CD40 70B, CD407 7B) /Subject (CMO S Quad ExclusiveOR and ExclusiveNOR Gate) /Autho r () /Keywords (Harris Semicon- ductor, CD400 0, metal gate, CMOS , pdip, cerdip, mil,

Data sheet acquired from Harris Semiconductor SCHS055

January 1998

CD4070B,

CD4077B

CMOS Quad Exclusive-OR

and Exclusive-NOR Gate

Features

•High-Voltage Types (20V Rating)

•CD4070B - Quad Exclusive-OR Gate

•CD4077B - Quad Exclusive-NOR Gate

•Medium Speed Operation

-tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF

•100% Tested for Quiescent Current at 20V

•Standardized Symmetrical Output Characteristics

•5V, 10V and 15V Parametric Ratings

•Maximum Input Current of 1μA at 18V Over Full

Package Temperature Range

-100nA at 18V and 25oC

•Noise Margin (Over Full Package Temperature Range)

-1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V

•Meets All Requirements of JEDEC Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices

Applications

•Logical Comparators

•Adders/Subtractors

•Parity Generators and Checkers

Description

The Harris CD4070B contains four independent ExclusiveOR gates. The Harris CD4077B contains four independent Exclusive-NOR gates.

The CD4070B and CD4077B provide the system designer with a means for direct implementation of the Exclusive-OR and Exclusive-NOR functions, respectively.

Ordering Information

	TEMP.		PKG.
PART NUMBER	RANGE (oC)	PACKAGE	NO.
CD4070BE	-55 to 125	14 Ld PDIP	E14.3
CD4077BE	-55 to 125	14 Ld PDIP	E14.3
CD4070BF	-55 to 125	14 Ld CERDIP	F14.3
CD4077BF	-55 to 125	14 Ld CERDIP	F14.3
CD4070BM	-55 to 125	14 Ld SOIC	M14.15
CD4077BM	-55 to 125	14 Ld SOIC	M14.15

Pinouts

		CD4070B							CD4077B
	(PDIP, CERDIP, SOIC)							(PDIP, CERDIP, SOIC)
		TOP VIEW							TOP VIEW
A				VDD		A					VDD
	1		14					1		14
B				H		B					H
	2		13					2		13
J = A Å B				G	J =						G
	3		12			A Å B		3		12
K = C Å D				M = G Å H	K =						M =
	4		11			C Å D		4		11			G Å H
				L = E Å F							L =
C	5		10			C		5		10		E Å F
D				F		D					F
	6		9					6		9
VSS				E		VSS					E
	7		8					7		8

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.		File Number 910.1
Copyright © Harris Corporation 1998	1

CD4070B, CD4077B

Functional Diagrams

CD4070B

	A	1	3
		2
J = A Å B	B		J
K = C Å D	C	5	4
M = G Å H	D	6	K
L = E Å F	E	8	10
		9
VSS = 7	F		L
VDD = 14	G	12	11 M
		13
	H

	VDD
			VDD
B †	p		p
2(5,9,12)		n
	n
	VSS		p
				p
	VDD		p	J
A †	p		n	3(4,10,11)
				n
1(6,8,13)
	n
	VSS		VDD	VSS
† INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
			VSS

CD4077B

B †

2(5,9,12)

A †

1(6,8,13)

				1
				A
				2
				B
	J =	A Å B		5
				C
	K = C Å D
				6
				D
				8
	M = G Å H			E
				9
	L = E Å F
				F
				G 12
				H 13

VDD

p
n	n
VSS	p
VDD
p
n

3

J

4

K

10

L

11 M

VDD

p

n

p

J

n	3(4,10,11)
	n

VSS	VSS
	VDD

† INPUTS PROTECTED BY CMOS PROTECTION NETWORK

VSS

FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B

(1 OF 4 IDENTICAL GATES)

CD4070B TRUTH TABLE (1 OF 4 GATES)

	A	B	J
	0	0	0
	1	0	1
	0	1	1
	1	1	0
NOTE:
1	= High Level
0	= Low Level
J = A Å B

FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B

(1 OF 4 IDENTICAL GATES)

CD4077B TRUTH TABLE (1 OF 4 GATES)

			A	B	J
	0			0	1
	1			0	0
	0			1	0
	1			1	1
NOTE:
1	= High Level
0	= Low Level
J =
		A Å B

2

CD4070B, CD4077B

Absolute Maximum Ratings

DC Supply Voltage Range (VDD) . . . . . . . . . . . . . . . . . -0.5V to 20V Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5V to VDD 0.5V DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 10mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 3V to 18V

Thermal Information

Thermal Resistance (Typical, Note 1)	θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .	90	N/A
CERDIP Package . . . . . . . . . . . . . . . .	95	38
SOIC Package . . . . . . . . . . . . . . . . . . .	175	N/A
Maximum Junction Temperature (Hermetic Package or Die)175oC
Maximum Junction Temperature (Plastic Package) .		. . . . . . . 150oC
Maximum Storage Temperature Range . .	. . . . . . . .	-65oC to 150oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

						LIMITS AT INDICATED TEMPERATURES (oC)
	CONDITIONS									25
	VO	VIN		VDD
PARAMETER	(V)	(V)		(V)	-55	-40	85	125	MIN	TYP	MAX	UNITS
Quiescent Device Current	-	0, 5		5	0.25	0.25	7.5	7.5	-	0.01	0.25	μA
IDD Max
	-	0, 10		10	0.5	0.5	15	15	-	0.01	0.5	μA
	-	0, 15		15	1	1	30	30	-	0.01	1	μA
	-	0, 20		20	5	5	150	150	-	0.02	5	μA
Output Low (Sink) Current	0.4	0, 5		5	0.64	0.61	0.42	0.36	0.51	1	-	mA
IOL Min
	0.5	0, 10		10	1.6	1.5	1.1	0.9	1.3	2.6	-	mA
	1.5	0, 15		15	4.2	4	2.8	2.4	3.4	6.8	-	mA
Output High (Source) Current	4.6	0, 5		5	-0.64	-0.61	-0.42	-0.36	-0.51	-1	-	mA
IOH Min
	2.5	0, 5		5	-2	-1.8	-1.3	-1.15	-1.6	-3.2	-	mA
	9.5	0, 10		10	-1.6	-1.5	-1.1	-0.9	-1.3	-2.6	-	mA
	13.5	0, 15		15	-4.2	-4	-2.8	-2.4	-3.4	-6.8	-	mA
Output Voltage: Low Level,	-	0, 5		5	0.05	0.05	0.05	0.05	-	0	0.05	V
VOL Max
	-	0, 10		10	0.05	0.05	0.05	0.05	-	0	0.05	V
	-	0, 15		15	0.05	0.05	0.05	0.05	-	0	0.05	V
Output Voltage: High Level,	-	0, 5		5	4.95	4.95	4.95	4.95	4.95	5	-	V
VOH Min
	-	0, 10		10	9.95	9.95	9.95	9.95	9.95	10	-	V
	-	0, 15		15	14.95	14.95	14.95	14.95	14.95	15	-	V
Input Low Voltage,	0.5, 4.5	-		5	1.5	1.5	1.5	1.5	-	-	1.5	V
VIL Max
	1, 9	-		10	3	3	3	3	-	-	3	V
	1.5, 13.5	-		15	4	4	4	4	-	-	4	V
Input High Voltage,	0.5, 4.5	-		5	3.5	3.5	3.5	3.5	3.5	-	-	V
VIH Min
	1, 9	-		10	7	7	7	7	7	-	-	V
	1.5, 13.5	-		15	11	11	11	11	11	-	-	V
Input Current, IIN Max	-	0, 18		18	±0.1	±0.1	±1	±1	-	±10-5	±0.1	μA

3