August 1999
Revised October 1999
74ACT16245
16-Bit Transceiver with 3-STATE Outputs
General Description
The ACT16245 contains sixteen non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state.
Features
■Bidirectional non-inverting buffers
■Separate control logic for each byte
■16-bit version of the ACT245
■Outputs source/sink 24 mA
■TTL-compatible inputs
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACT16245SSC |
MS48A |
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide |
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74ACT16245MTD |
MTD48 |
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol |
Connection Diagram |
Pin Description
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Pin Names |
Description |
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n |
Output Enable Input (Active LOW) |
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OE |
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Transmit/Receive Input |
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T/R |
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A0–A15 |
Side A Inputs/Outputs |
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B0–B15 |
Side B Outputs/Inputs |
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FACTä is a trademark of Fairchild Semiconductor Corporation.
Outputs STATE-3 with Transceiver Bit-16 74ACT16245
© 1999 Fairchild Semiconductor Corporation |
DS500296 |
www.fairchildsemi.com |
74ACT16245
Functional Description
The ACT16245 contains sixteen non-inverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the T/R input is HIGH, then Bus A data is transmitted to Bus B. When the T/R input is LOW,
Bus B data is transmitted to Bus A. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each
byte. When OEn is LOW, the outputs are in 2-state mode.
When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs.
Truth Tables
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Inputs |
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Outputs |
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OE1 |
T/R1 |
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L |
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L |
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Bus B0–B7 Data to Bus A0–A7 |
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L |
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H |
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Bus A0–A7 Data to Bus B0–B7 |
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H |
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X |
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HIGH-Z State on A0–A7, B0–B7 |
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Inputs |
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Outputs |
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OE2 |
T/R2 |
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L |
L |
Bus B8–B15 Data to Bus A8–A15 |
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L |
H |
Bus A8–A15 Data to Bus B8–B15 |
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H |
X |
HIGH-Z State on A8–A15, B8–B15 |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
−0.5V to + 7.0V |
DC Input Diode Current (IIK) |
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VI = −0.5V |
−20 mA |
VI = VCC + 0.5V |
+20 mA |
DC Output Diode Current (IOK) |
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VO = −0.5V |
−20 mA |
VO = VCC +0.5V |
+20 mA |
DC Output Voltage (VO) |
−0.5V to VCC +0.5V |
DC Output Source/Sink Current (IO) |
± 50 mA |
DC VCC or Ground Current |
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per Output Pin |
± 50 mA |
Storage Temperature |
−65°C to +150°C |
Recommended Operating
Conditions
Supply Voltage (VCC) |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
−40°C to +85°C |
Minimum Input Edge Rate ( V/ t) |
125 mV/ns |
VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
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Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTä circuits outside databook specifications.
DC Electrical Characteristics
Symbol |
Parameter |
VCC |
TA = +25°C |
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TA = −40°C to+85°C |
Units |
Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH |
4.5 |
1.5 |
2.0 |
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2.0 |
V |
VOUT = 0.1V |
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Input Voltage |
5.5 |
1.5 |
2.0 |
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2.0 |
or VCC − 0.1V |
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VIL |
Maximum LOW |
4.5 |
1.5 |
0.8 |
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0.8 |
V |
VOUT = 0.1V |
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Input Voltage |
5.5 |
1.5 |
0.8 |
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0.8 |
or VCC − 0.1V |
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VOH |
Minimum HIGH |
4.5 |
4.49 |
4.4 |
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4.4 |
V |
IOUT = −50 μA |
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Output Voltage |
5.5 |
5.49 |
5.4 |
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5.4 |
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VIN = VIL or VIH |
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4.5 |
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3.86 |
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3.76 |
V |
IOH = −24 mA |
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5.5 |
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4.86 |
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4.76 |
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IOH = −24 mA (Note 2) |
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VOL |
Maximum LOW |
4.5 |
0.001 |
0.1 |
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0.1 |
V |
IOUT = 50 μA |
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Output Voltage |
5.5 |
0.001 |
0.1 |
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0.1 |
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VIN = VIL or VIH |
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4.5 |
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0.36 |
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0.44 |
V |
IOL = 24 mA |
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5.5 |
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0.36 |
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0.44 |
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IOL = 24 mA (Note 2) |
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IOZT |
Maximum I/O |
5.5 |
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±0.5 |
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±5.0 |
μA |
VI = VIL, VIH |
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Leakage Current |
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VO = VCC, GND |
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IIN |
Maximum Input |
5.5 |
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±0.1 |
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±1.0 |
μA |
VI = VCC, GND |
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Leakage Current |
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ICCT |
Maximum ICC/Input |
5.5 |
0.6 |
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1.5 |
mA |
VI = VCC −2.1V |
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ICC |
Max Quiescent |
5.5 |
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8.0 |
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80.0 |
μA |
VIN = VCC or GND |
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Supply Current |
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IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = 1.65V Max |
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IOHD |
Output Current (Note 3) |
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−75 |
mA |
VOHD = 3.85V Min |
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Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
74ACT16245
3 |
www.fairchildsemi.com |
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