Fairchild Semiconductor 74ACT161SJX, 74ACT161SJ, 74ACT161SCX, 74ACT161SC, 74ACT161PC Datasheet
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November 1988
Revised November 1999
74AC161 • 74ACT161
Synchronous Presettable Binary Counter
General Description
The AC/ACT161 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The AC/ACT161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW.
Features
■ICC reduced by 50%
■Synchronous counting and loading
■High-speed synchronous expansion
■Typical count rate of 125 MHz
■Outputs source/sink 24 mA
■ACT161 has TTL-compatible inputs
Ordering Code:
Order Number |
Package Number |
Package Description |
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74AC161SC |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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74AC161SJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74AC161MTC |
MTC16 |
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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74AC161PC |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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74ACT161SC |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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74ACT161SJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74ACT161MTC |
MTC16 |
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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74ACT161PC |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Descriptions
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Pin Names |
Description |
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CEP |
Count Enable Parallel Input |
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CET |
Count Enable Trickle Input |
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CP |
Clock Pulse Input |
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Asynchronous Master Reset Input |
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MR |
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P0–P3 |
Parallel Data Inputs |
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Parallel Enable Inputs |
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PE |
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Q0–Q3 |
Flip-Flop Outputs |
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TC |
Terminal Count Output |
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FACT is a trademark of Fairchild Semiconductor Corporation.
Counter Binary Presettable Synchronous 74ACT161 • 74AC161
© 1999 Fairchild Semiconductor Corporation |
DS009931 |
www.fairchildsemi.com |
74AC161 • 74ACT161
Functional Description
The AC/ACT161 count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the AC/ACT161) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset, parallel load, count-up and hold. Five control inputs— Master Reset, Parallel Enable (PE ), Count Enable Parallel (CEP) and Count Enable Trickle (CET)— determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops
on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting.
The AC/ACT161 use D-type edge-triggered flip-flops and changing the PE, CEP, and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways.
Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle requires 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that lim-
its the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters.
Logic Equations: Count Enable = CEP • CET • PE TC = Q0 • Q1 • Q2 • Q3 • CET
Mode Select Table
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CET |
CEP |
Action on the Rising |
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PE |
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Clock Edge ( ) |
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X |
X |
X |
Reset (Clear) |
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L |
X |
X |
Load (Pn→ Qn) |
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H |
H |
H |
Count (Increment) |
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H |
L |
X |
No Change (Hold) |
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H |
X |
L |
No Change (Hold) |
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H = |
HIGH Voltage Level |
L = |
LOW Voltage Level |
X = |
Immaterial |
State Diagram
FIGURE 1. Multistage Counter with Ripple Carry
FIGURE 2. Multistage Counter with Lookahead Carry
www.fairchildsemi.com |
2 |
Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACT161 • 74AC161
3 |
www.fairchildsemi.com |
74AC161 • 74ACT161
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
− 0.5V to + 7.0V |
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DC Input Diode Current (IIK) |
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VI = |
− 0.5V |
− 20 mA |
VI = |
VCC + 0.5V |
+ 20 mA |
DC Input Voltage (VI) |
− 0.5V to VCC + 0.5V |
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DC Output Diode Current (IOK) |
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VO = |
− 0.5V |
− 20 mA |
VO = |
VCC + 0.5V |
+ 20 mA |
DC Output Voltage (VO) |
− 0.5V to VCC + 0.5V |
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DC Output Source |
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or Sink Current (IO) |
± 50 mA |
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DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
± 50 mA |
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Storage Temperature (TSTG) |
− 65° C to + 150° C |
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Junction Temperature (TJ) |
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PDIP |
140° C |
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Recommended Operating
Conditions
Supply Voltage (VCC) |
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AC |
2.0V to 6.0V |
ACT |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
− 40° C to + 85° C |
Minimum Input Edge Rate (∆ V/∆ t) |
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AC Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.3V, 4.5V, 5.5V |
125 mV/ns |
Minimum Input Edge Rate (∆ V/∆ t) |
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ACT Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol |
Parameter |
VCC |
TA = + 25° C |
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TA = − 40° C to + 85° C |
Units |
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Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
3.0 |
1.5 |
2.1 |
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2.1 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
3.15 |
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3.15 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
3.85 |
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3.85 |
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VIL |
Maximum LOW Level |
3.0 |
1.5 |
0.9 |
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0.9 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
1.35 |
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1.35 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
1.65 |
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1.65 |
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VOH |
Minimum HIGH Level |
3.0 |
2.99 |
2.9 |
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2.9 |
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Output Voltage |
4.5 |
4.49 |
4.4 |
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4.4 |
V |
IOUT = |
− |
50 µ A |
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5.5 |
5.49 |
5.4 |
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5.4 |
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VIN = |
VIL or VIH |
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3.0 |
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2.56 |
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2.46 |
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IOH = |
− |
12 mA |
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4.5 |
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3.86 |
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3.76 |
V |
IOH = |
− |
24 mA |
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5.5 |
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4.86 |
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4.76 |
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IOH = |
− 24 mA (Note 2) |
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VOL |
Maximum LOW Level |
3.0 |
0.002 |
0.1 |
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0.1 |
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Output Voltage |
4.5 |
0.001 |
0.1 |
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0.1 |
V |
IOUT = |
50 µ A |
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5.5 |
0.001 |
0.1 |
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0.1 |
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VIN = |
VIL or VIH |
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3.0 |
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0.36 |
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0.44 |
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IOL = |
12 mA |
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4.5 |
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0.36 |
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0.44 |
V |
IOL = |
24 mA |
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5.5 |
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0.36 |
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0.44 |
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IOL = |
24 mA (Note 2) |
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IIN |
Maximum Input |
5.5 |
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± 0.1 |
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± 1.0 |
µ A |
VI = |
VCC, GND |
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(Note 4) |
Leakage Current |
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IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = |
1.65V Max |
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IOHD |
Output Current (Note 3) |
5.5 |
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− 75 |
mA |
VOHD = |
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3.85V Min |
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ICC |
Maximum Quiescent |
5.5 |
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4.0 |
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40.0 |
µ A |
VIN = |
VCC |
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(Note 4) |
Supply Current |
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or GND |
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Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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4 |
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