MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
16 |
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4 |
Bit |
Register |
File |
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The MC10H145 is a 16 x 4 bit register file. The active-low chip select allows |
MC10H145 |
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easy expansion. |
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The operating mode of the register file is controlled by the WE input. When |
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WE is ªlowº the device is in the write mode, the outputs are ªlowº and the data |
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present at Dn input is stored at the selected address, when WE is ªhigh,º the |
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device is in the read mode Ð the data state at the selected location is present |
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at the Qn outputs. |
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L SUFFIX |
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• Address Access Time, 4.5 ns Typical |
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CERAMIC PACKAGE |
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• Power Dissipation, 700 mW Typical |
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CASE 620±10 |
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• Improved Noise Margin 150 mV (Over Operating Voltage and |
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Temperature Range) |
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P SUFFIX |
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• Voltage Compensated |
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PLASTIC PACKAGE |
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• MECL 10K-Compatible |
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CASE 648±08 |
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FN SUFFIX |
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MAXIMUM RATINGS |
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PLCC |
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CASE 775±02 |
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Characteristic |
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Symbol |
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Rating |
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Unit |
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Power Supply (VCC = 0) |
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VEE |
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±8.0 to 0 |
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Vdc |
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TRUTH TABLE |
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Input Voltage (VCC = 0) |
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VI |
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0 to VEE |
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Vdc |
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Output Current Ð Continuous |
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Iout |
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50 |
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mA |
MODE |
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INPUT |
OUTPUT |
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Ð Surge |
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100 |
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Operating Temperature Range |
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TA |
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0 to +75 |
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° |
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CS |
WE |
Dn |
Qn |
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C |
Write ª0º |
L |
L |
L |
L |
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Storage Temperature Range Ð Plastic |
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Tstg |
±55 to +150 |
°C |
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Write ª1º |
L |
L |
H |
L |
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Ð Ceramic |
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±55 to +165 |
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ELECTRICAL CHARACTERISTICS (VEE = ±5.2 V ±5%) (See Note) |
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Read |
L |
H |
X |
Q |
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Disabled |
H |
X |
X |
L |
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0° |
25° |
75° |
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Characteristic |
Symbol |
Unit |
Q-State of Addressed Cell |
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Min |
Max |
Min |
Max |
Min |
Max |
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Power Supply Current |
IE |
Ð |
160 |
Ð |
163 |
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165 |
mA |
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Input Current High |
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IinH |
Ð |
375 |
Ð |
220 |
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220 |
μA |
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DIP |
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Input Current Low |
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IinL |
0.5 |
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0.5 |
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0.3 |
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μA |
PIN ASSIGNMENT |
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High Output Voltage |
VOH |
±1.02 |
±0.84 |
±0.98 |
±0.81 |
±0.92 |
±0.735 |
Vdc |
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Low Output Voltage |
VOL |
±1.95 |
±1.63 |
±1.95 |
±1.63 |
±1.95 |
±1.60 |
Vdc |
Q1 |
1 |
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16 |
VCC |
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High Input Voltage |
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VIH |
±1.17 |
±0.84 |
±1.13 |
±0.81 |
±1.07 |
±0.735 |
Vdc |
Q0 |
2 |
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15 |
Q2 |
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Low Input Voltage |
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VIL |
±1.95 |
±1.48 |
±1.95 |
±1.48 |
±1.95 |
±1.45 |
Vdc |
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CS |
3 |
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14 |
Q3 |
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NOTE: |
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Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, |
D1 |
4 |
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13 |
WE |
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after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed |
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circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through |
D0 |
5 |
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12 |
D3 |
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a 50-ohm resistor to ±2.0 volts. |
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A3 |
6 |
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11 |
D2 |
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A2 |
7 |
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10 |
A0 |
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VEE |
8 |
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9 |
A1 |
Pin assignment is for Dual±in±Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6±11 of the Motorola MECL Data
Book (DL122/D).
3/93
Motorola, Inc. 1996 |
2±233 |
REV 5 |
MC10H145
AC PARAMETERS
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MC10H145 |
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TA = 0 to +75°C, |
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VEE = ±5.2 Vdc ±5% |
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Characteristics |
Symbol |
Min |
Max |
Unit |
Conditions |
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Read Mode |
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ns |
Measured from 50% of input to 50% |
Chip Select Access Time |
tACS |
0 |
4.0 |
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of output. See Note 2. |
Chip Select Recovery Time |
tRCS |
0 |
4.0 |
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Address Access Time |
tAA |
0 |
6.0 |
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Write Mode |
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ns |
tWSA = 3.5 ns |
Write Pulse Width |
tW |
6.0 |
Ð |
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Measured at 50% of input to 50% of |
Data Setup Time Prior to Write |
tWSD |
0 |
Ð |
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output. tW = 6.0 ns. |
Data Hold Time After Write |
tWHD |
1.5 |
Ð |
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Address Setup Time Prior to Write |
tWSA |
3.5 |
Ð |
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Address Hold Time After Write |
tWHA |
1.5 |
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Chip Select Setup Time Prior to Write |
tWSCS |
0 |
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Chip Select Hold Time After Write |
tWHCS |
1.5 |
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Write Disable Time |
tWS |
1.0 |
4.0 |
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Write Recovery Time |
tWR |
1.0 |
4.0 |
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Chip Enable Strobe Mode |
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ns |
Guaranteed but not tested on |
Data Setup Prior to Chip Select |
tCSD |
0 |
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standard product. See Figure 1. |
Write Enable Setup Prior to Chip Select |
tCSW |
0 |
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Address Setup Prior to Chip Select |
tCSA |
0 |
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Data Hold Time After Chip Select |
tCHD |
1.0 |
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Write Enable Hold Time After Chip Select |
tCHW |
0 |
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Address Hold Time After Chip Select |
tCHA |
2.0 |
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Chip Select Minimum Pulse Width |
tCS |
4.0 |
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Rise and Fall Time |
tr, tf |
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ns |
Measured between 20% and 80% |
Address to Output |
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0.6 |
2.5 |
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points. |
CS to Output |
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0.6 |
2.5 |
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Capacitance |
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pF |
Measured with a pulse technique. |
Input Capacitance |
Cin |
Ð |
6.0 |
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Output Capacitance |
Cout |
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8.0 |
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NOTES: 1. Test circuit characteristics: RT = 50 Ω, MC10H145. CL p5.0 pF (including jig and Stray Capacitance). Delay should be derated 30 ps/pF for capacitive loads up to 50 pF.
2.The maximum Address Access Time is guaranteed to be the worst-case bit in the memory.
3.For proper use of MECL in a system environment, consult MECL System Design Handbook.
FIGURE 1 Ð CHIP ENABLE STROBE MODE
A |
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TCSD |
TCHA |
DIN |
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TCHD |
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WE |
TCSW |
TCHW |
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TCSA |
TCS |
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CS |
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MOTOROLA |
2±234 |
MECL Data |
DL122 Ð Rev 6
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