MOTOROLA MC10H135FN, MC10H135FNR2, MC10H135M, MC10H135ML1 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Dual

J-K

Master-Slave

MC10H135

Flip-Flop

The MC10H135 is a dual J±K master±slave flip±flop. The device is provided

L SUFFIX

with an asynchronous set(s) and reset(R). These set and reset inputs overide

CERAMIC PACKAGE

CASE 620±10

the clock.

A common clock is provided with separate J±K inputs. When the clock is

P SUFFIX

static, the JK inputs do not effect the output. The output states of the flip flop

PLASTIC PACKAGE

change on the positive transition of the clock.

CASE 648±08

• Propagation delay, 1.5 ns Typical •

Improved Noise Margin 150

FN SUFFIX

PLCC

• Power Dissipation, 280 mW

mV (Over Operating Voltage

CASE 775±02

Typical/Pkg. (No Load)

and Temperature Range)

• ftog 250 MHz Max•

Voltage Compensated

• MECL 10K±Compatible

LOGIC DIAGRAM

MAXIMUM RATINGS

S1

5

2

J1

7

Q1

Characteristic

Symbol

Rating

Unit

Power Supply (VCC = 0)

VEE

±8.0 to 0

Vdc

K1

6

Q1

3

Input Voltage (VCC = 0)

VI

0 to VEE

Vdc

R1

4

VCC1 =

PIN 1

Output Current Ð Continuous

I

50

mA

C

9

VCC2 =

PIN 16

Ð Surge

out

100

S2 12

VEE =

PIN 8

Operating Temperature Range

TA

0 to +75

°C

J2 10

Q2

15

Storage Temperature Range Ð Plastic

Tstg

±55 to +150

°C

Ð Ceramic

±55 to +165

°

K2 11

Q2

14

C

ELECTRICAL CHARACTERISTICS (VEE = ±5.2 V ±5%) (See Note)

R2 13

0°

25°

75°

RS TRUTH TABLE

CLOCK J±K TRUTH TABLE*

Characteristic

Symbol

Min

Max

Min

Max

Min

Max

Unit

R

S

Qn + 1

J

K

Qn + 1

L

L

Qn

L

L

Qn

Power Supply Current

IE

Ð

75

Ð

68

Ð

75

mA

L

H

H

H

L

L

Input Current High

IinH

μA

H

L

L

L

H

H

Pins 6, 7, 10, 11

Ð

460

Ð

285

Ð

285

H

H

N.D.

H

H

Qn

Pins 4, 5, 12, 13

Ð

800

Ð

500

Ð

500

N.D. = Not Defined

*Output states change on

Pin 9

Ð

675

Ð

420

Ð

420

positive

transition of clock

for

J±K input

condition

Input Current Low

IinL

0.5

Ð

0.5

Ð

0.3

Ð

A

μ

present.

High Output Voltage

VOH

±1.02

±0.84

±0.98

±0.81

±0.92

±0.735

Vdc

DIP PIN ASSIGNMENT

Low Output Voltage

VOL

±1.95

±1.63

±1.95

±1.63

±1.95

±1.60

Vdc

High Input Voltage

VIH

±1.17

±0.84

±1.13

±0.81

±1.07

±0.735

Vdc

VCC1

1

16

VCC2

Low Input Voltage

VIL

±1.95

±1.48

±1.95

±1.48

±1.95

±1.45

Vdc

2

15

Q1

Q2

AC PARAMETERS

3

14

Q1

Q2

Propagation Delay

tpd

0.7

2.6

0.7

2.6

0.7

2.6

ns

R1

4

13

R2

Set, Reset, Clock

S1

5

12

S2

Rise Time

tr

0.7

2.2

0.7

2.2

0.7

2.2

ns

6

11

K1

K2

Fall Time

tf

0.7

2.2

0.7

2.2

0.7

2.2

ns

7

10

J1

J2

Set±up Time

tset

1.5

Ð

1.5

Ð

1.5

Ð

ns

VEE

8

9

C

Hold Time

thold

1.0

Ð

1.0

Ð

1.0

Ð

ns

Toggle Frequency

ftog

250

Ð

250

Ð

250

Ð

MHz

Pin assignment is for Dual±in±Line Package.

NOTE:

For PLCC pin assignment, see the Pin Conversion

Tables on page 6±11 of the Motorola MECL Data

Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,

Book (DL122/D).

after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit

board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a

50±ohm resistor to ±2.0 volts.

9/96

Motorola, Inc. 1996

2±89

REV 6