Integrated Device Technology Inc IDT7015S15G, IDT7015S15J, IDT7015S15PF, IDT7015S17G, IDT7015S17J Datasheet
...
HIGH-SPEED |
IDT7015S/L |
8K x 9 DUAL-PORT |
|
STATIC RAM |
|
Integrated Device Technology, Inc.
FEATURES:
•True Dual-Ported memory cells which allow simultaneous access of the same memory location
•High-speed access
—Military: 20/25/35ns (max.)
—Commercial: 12/15/17/20/25/35ns (max.)
•Low-power operation
—IDT7015S
Active: 750mW (typ.) Standby: 5mW (typ.)
—IDT7015L
Active: 750mW (typ.) Standby: 1mW (typ.)
•IDT7015 easily expands data bus width to 18 bits or more using the Master/Slave select when cascading more than one device
•M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave
•Interrupt and Busy Flags
•On-chip port arbitration logic
•Full on-chip hardware support of semaphore signaling between ports
•Fully asynchronous operation from either port
•Devices are capable of withstanding greater than 2001V electrostatic discharge
•TTL-compatible, single 5V (±10%) power supply
•Available in ceramic 68-pin PGA, 68-pin PLCC, and an 80-pin TQFP
•Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications
DESCRIPTION:
The IDT7015 is a high-speed 8K x 9 Dual-Port Static RAMs. The IDT7015 is designed to be used as stand-alone Dual-Port RAM or as a combination MASTER/SLAVE DualPort RAM for 18-bit-or-more word systems. Using the IDT
FUNCTIONAL BLOCK DIAGRAM
OEL
CEL
R/WL
I/O0L- I/O8L 
I/O |
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I/O |
Control |
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Control |
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(1,2)
BUSYL
A12L |
Address |
MEMORY |
Address |
A0L |
Decoder |
ARRAY |
Decoder |
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13 |
13 |
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ARBITRATION |
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CEL |
INTERRUPT |
CER |
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SEMAPHORE |
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OEL |
OER |
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LOGIC |
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R/WL |
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R/WR |
SEML |
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M/S |
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(2) |
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INTL |
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NOTES:
1.In MASTER mode: BUSY is an output and is a push-pull driver In SLAVE mode: BUSY is input.
2.BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
OER
CER
R/WR
I/O0R-I/O8R
(1,2)
BUSYR
A12R
A0R
SEMR
(2)
INTR
2954 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
OCTOBER 1996 |
|
©1996 Integrated Device Technology, Inc. |
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391. |
DSC-2954/2 |
6.12 |
1 |
IDT7015S/L |
|
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
MASTER/SLAVE Dual-Port RAM approach in 18-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 750mW of power.
The IDT7015 is packaged in a ceramic 68-pin PGA, a 64pin PLCC and an 80-pin TQFP (Thin Quad FlatPack). Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
PIN CONFIGURATIONS (1,2)
INDEX
A6L
A7L
A8L
A9L
A10L
A11L
A12L
VCC
N/C
N/C
CEL
SEM L
R/WL
OEL
I/O8L
I/O0L
I/O1L
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I/O2L |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
68 67 66 65 64 |
63 62 61 |
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A5L |
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10 |
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60 |
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I/O3L |
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11 |
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59 |
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A4L |
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I/O4L |
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12 |
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58 |
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A3L |
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I/O5L |
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13 |
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57 |
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A2L |
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GND |
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14 |
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IDT7015 |
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56 |
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A1L |
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I/O6L |
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15 |
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55 |
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A0L |
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(8K x 9) |
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I/O7L |
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16 |
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J68-1 |
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54 |
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INTL |
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VCC |
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17 |
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53 |
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BUSY |
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GND |
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PLCC |
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L |
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18 |
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52 |
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GND |
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I/O0R |
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19 |
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(3) |
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51 |
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M/S |
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I/O1R |
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20 |
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TOP VIEW |
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50 |
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BUSYR |
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I/O2R |
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21 |
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49 |
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INT |
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VCC |
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R |
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22 |
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48 |
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A0R |
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I/O3R |
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23 |
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47 |
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A1R |
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I/O4R |
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24 |
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46 |
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A2R |
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I/O5R |
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45 |
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A3R |
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I/O6R |
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44 |
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A4R |
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27 |
28 29 |
30 31 |
32 33 34 35 |
36 37 38 39 |
40 41 42 43 |
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A5R
A6R
A7R
A8R
A9R
A10R
A11R
A12R
GND
N/C
N/C
CER
SEMR
R/WR
OER
I/O8R
I/O7R
NOTES:
1.All VCC pins must be connected to power supply.
2.All GND pins must be connected to ground supply.
3.This text does not imply orientation of Part-Mark.
2954 drw 02
PIN NAMES
Left Port |
|
Right Port |
Names |
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|
CEL |
|
CER |
Chip Enable |
R/WL |
|
R/WR |
Read/Write Enable |
OEL |
|
OER |
Output Enable |
A0L – A12L |
|
A0R – A12R |
Address |
I/O0L – I/O8L |
|
I/O0R – I/O8R |
Data Input/Output |
SEML |
|
SEMR |
Semaphore Enable |
INTL |
|
INTR |
Interrupt Flag |
BUSYL |
|
BUSYR |
Busy Flag |
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M/S |
Master or Slave Select |
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VCC |
Power |
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GND |
Ground |
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2954 tbl 01 |
6.12 |
2 |
IDT7015S/L |
|
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
PIN CONFIGURATIONS (CON'T.) (1,2)
INDEX
NC
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
NC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80 I/O1L
21
7R I/O
I/O0L |
I/O8L |
OEL |
R/WL |
SEM L |
CEL |
NC |
NC |
NC |
VCC |
A12L |
A11L |
A10L |
A9L |
A8L |
A7L |
A6L |
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NC |
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79 |
78 |
77 |
76 |
75 |
74 |
73 |
72 |
71 |
70 |
69 |
68 |
67 |
66 |
65 |
64 |
63 |
62 |
|||||||||||||||||
IDT7015 (8K X 9)
PN-80
TQFP
TOP VIEW(3)
22 |
23 |
24 |
25 |
26 |
27 |
28 |
29 |
30 |
31 |
32 |
33 |
34 |
35 |
36 |
37 |
38 |
39 |
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I/O8R |
OER |
R/WR |
SEMR |
CER |
NC |
NC |
NC |
GND |
A12R |
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A11R |
A10R |
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A9R |
A8R |
A7R |
A6R |
A5R |
NC |
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61 NC
NC 40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
NC
NC
2954 drw 03
11 |
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51 |
50 |
48 |
46 |
44 |
42 |
40 |
38 |
36 |
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A5L |
A4L |
A2L |
A0L |
BUSYL |
M/S |
INTR |
A1R |
A3R |
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10 |
53 |
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52 |
49 |
47 |
45 |
43 |
41 |
39 |
37 |
35 |
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34 |
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A7L |
A6L |
A3L |
A1L |
INTL |
GND |
BUSYR |
A0R |
A2R |
A4R |
A5R |
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09 |
55 |
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54 |
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32 |
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33 |
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A9L |
A8L |
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A7R |
A6R |
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08 |
57 |
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56 |
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30 |
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31 |
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A11L |
A10L |
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A9R |
A8R |
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07 |
59 |
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58 |
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IDT7015 |
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28 |
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29 |
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A11R |
A10R |
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VCC |
A12L |
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(8K x 9) |
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G68-1 |
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61 |
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60 |
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26 |
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27 |
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06 |
N/C |
N/C |
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68-PIN PGA |
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GND |
A12R |
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(3) |
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05 |
63 |
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62 |
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TOP VIEW |
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24 |
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25 |
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SEML |
CEL |
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N/C |
N/C |
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04 |
65 |
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64 |
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22 |
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23 |
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OE |
L |
R/WL |
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SEMR |
CE |
R |
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03 |
67 |
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66 |
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20 |
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21 |
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I/O0L |
I/O8L |
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OE |
R |
R/WR |
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02 |
68 |
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1 |
3 |
5 |
7 |
9 |
11 |
13 |
15 |
18 |
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19 |
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I/O1L |
I/O2L |
I/O4L |
GND |
I/O7L |
GND |
I/O1R |
VCC |
I/O4R |
I/O7R |
I/O8R |
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01 |
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2 |
4 |
6 |
8 |
10 |
12 |
14 |
16 |
17 |
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I/O3L |
I/O5L |
I/O6L |
VCC |
I/O0R |
I/O2R |
I/O3R |
I/O5R |
I/O6R |
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A |
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B |
C |
D |
E |
F |
G |
H |
J |
K |
L |
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INDEX
NOTES:
2954 drw 04
1.All Vcc must be connected to power supply.
2.All GND must be connected to ground supply.
3.This text does not imply orientation of Part-Mark.
6.12 |
3 |
IDT7015S/L |
|
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
TRUTH TABLE: NON-CONTENTION READ/WRITE CONTROL
|
Inputs(1) |
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Outputs |
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CE |
R/W |
OE |
SEM |
I/O0-8 |
Mode |
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H |
X |
X |
H |
High-Z |
Deselected: Power-Down |
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L |
L |
X |
H |
DATAIN |
Write to Memory |
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L |
H |
L |
H |
DATAOUT |
Read Memory |
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X |
X |
H |
X |
High-Z |
Outputs Disabled |
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NOTE: |
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2954 tbl 02 |
1.Condition: A0L — A12L is not equal to A0R — A12R.
TRUTH TABLE: SEMAPHORE READ/WRITE CONTROL(1)
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Inputs |
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Outputs |
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CE |
R/W |
OE |
SEM |
I/O0-8 |
Mode |
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H |
H |
L |
L |
DATAOUT |
Read Semaphore Flag Data Out (I/O0-8) |
H |
u |
X |
L |
DATAIN |
Write I/O0 into Semaphore Flag |
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L |
X |
X |
L |
— |
Not Allowed |
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NOTE: |
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2954 tbl 03 |
1. There are eight semaphore flags written to via I/O0 and read from I/O0-8 . These eight semaphores are addressed by A0 - A2.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Rating |
Commercial |
Military |
Unit |
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VTERM(2) |
Terminal Voltage |
–0.5 to +7.0 |
–0.5 to +7.0 |
V |
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with Respect |
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to GND |
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TA |
Operating |
0 to +70 |
–55 to +125 |
°C |
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Temperature |
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TBIAS |
Temperature |
–55 to +125 |
–65 to +135 |
°C |
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Under Bias |
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TSTG |
Storage |
–55 to +125 |
–65 to +150 |
°C |
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Temperature |
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IOUT |
DC Output |
50 |
50 |
mA |
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Current |
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NOTES: |
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2954 tbl 04 |
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1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.5V.
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
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Ambient |
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Grade |
Temperature |
GND |
VCC |
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Military |
–55°C to +125°C |
0V |
5.0V ± 10% |
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Commercial |
0°C to +70°C |
0V |
5.0V ± 10% |
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2954 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
Symbol |
Parameter |
Min. |
Typ. |
Max. |
Unit |
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VCC |
Supply Voltage |
4.5 |
5.0 |
5.5 |
V |
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GND |
Supply Voltage |
0 |
0 |
0 |
V |
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VIH |
Input High Voltage |
2.2 |
— |
6.0(2) |
V |
VIL |
Input Low Voltage |
–0.5(1) |
— |
0.8 |
V |
NOTES: |
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2954 tbl 06 |
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1.VIL > -1.5V for pulse width less than 10ns.
2.VTERM must not exceed Vcc + 0.5V.
CAPACITANCE(1)
(TA = +25°C, f = 1.0MHz) TQFP ONLY
Symbol |
Parameter |
Conditions(2) |
Max. |
Unit |
CIN |
Input Capacitance |
VIN = 3dV |
9 |
pF |
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COUT |
Output |
VOUT = 3dV |
10 |
pF |
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Capacitance |
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NOTES:
1.This parameter is determined by device characteristics but is not production tested.
2.3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V .
6.12 |
4 |
IDT7015S/L |
|
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
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7015S |
7015L |
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Symbol |
Parameter |
Test Conditions |
Min. |
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Max. |
Min. |
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Max. |
Unit |
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|ILI| |
Input Leakage Current(1) |
VCC = 5.5V, VIN = 0V to VCC |
— |
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10 |
— |
|
5 |
μA |
|ILO| |
Output Leakage Current |
CE = VIH, VOUT = 0V to VCC |
— |
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10 |
— |
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5 |
μA |
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VOL |
Output Low Voltage |
IOL = 4mA |
— |
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0.4 |
— |
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0.4 |
V |
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VOH |
Output High Voltage |
IOH = -4mA |
2.4 |
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— |
2.4 |
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— |
V |
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NOTE: |
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2954 tbl 08 |
1. At Vcc < 2.0V, Input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE |
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OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) |
(VCC = 5.0V ± 10%) |
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7015X12 |
7015X15 |
7015X17 |
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Test |
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Com'l. Only |
Com'l. Only |
Com'l. Only |
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Symbol |
Parameter |
Condition |
Version |
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Typ.(2) |
Max. |
Typ.(2) |
Max. |
Typ.(2) Max. |
Unit |
||
ICC |
Dynamic Operating |
CE = VIL, Outputs Open |
MIL. |
S |
— |
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— |
— |
— |
— |
— |
mA |
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Current |
SEM = VIH |
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L |
— |
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— |
— |
— |
— |
— |
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(Both Ports Active) |
f = fMAX(3) |
COM’L. |
S |
170 |
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325 |
170 |
310 |
170 |
310 |
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L |
170 |
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275 |
170 |
260 |
170 |
260 |
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ISB1 |
Standby Current |
CER = CEL = VIH |
MIL. |
S |
— |
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— |
— |
— |
— |
— |
mA |
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(Both Ports — TTL |
SEMR = SEML = VIH |
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L |
— |
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— |
— |
— |
— |
— |
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f = fMAX(3) |
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Level Inputs) |
COM’L. |
S |
25 |
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70 |
25 |
60 |
25 |
60 |
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L |
25 |
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60 |
25 |
50 |
25 |
50 |
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ISB2 |
Standby Current |
CE"A"=VIL and CE"B" = VIH(5) |
MIL. |
S |
— |
|
— |
— |
— |
— |
— |
mA |
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(One Port — TTL |
Active Port Outputs Open |
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L |
— |
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— |
— |
— |
— |
— |
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Level Inputs) |
f = fMAX(3) |
COM’L. |
S |
105 |
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200 |
105 |
190 |
105 |
190 |
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SEMR = SEML = VIH |
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L |
105 |
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170 |
105 |
160 |
109 |
160 |
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ISB3 |
Full Standby Current |
Both Ports CEL and |
MIL. |
S |
— |
|
— |
— |
— |
— |
— |
mA |
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(Both Ports — All |
CER > VCC - 0.2V |
|
L |
— |
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— |
— |
— |
— |
— |
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CMOS Level Inputs) |
VIN > VCC - 0.2V or |
COM’L. |
S |
1.0 |
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15 |
1.0 |
15 |
1.0 |
15 |
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VIN < 0.2V, f = 0(4) |
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L |
0.2 |
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5 |
0.2 |
5 |
0.2 |
5 |
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SEMR = SEML > VCC - 0.2V |
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ISB4 |
Full Standby Current |
CE"A"< 0.2V and |
MIL. |
S |
— |
|
— |
— |
— |
— |
— |
mA |
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(One Port — All |
CE"B" > VCC - 0.2V(5) |
|
L |
— |
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— |
— |
— |
— |
— |
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CMOS Level Inputs) |
SEMR = SEML > VCC - 0.2V |
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VIN > VCC - 0.2V or |
COM’L. |
S |
100 |
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180 |
100 |
170 |
100 |
170 |
mA |
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VIN < 0.2V |
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L |
100 |
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150 |
100 |
140 |
100 |
140 |
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Active Port Outputs Open, |
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f = fMAX(3) |
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NOTES: |
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2954 tbl 09 |
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1."X" in part numbers indicates power rating (S or L).
2.VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA(typ.)
3.At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4.f = 0 means no address or control lines change.
5.Port "A" may be either left or right port. Port "B" is the opposite of port "A".
6.12 |
5 |
IDT7015S/L |
|
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Cont'd) (VCC = 5.0V ± 10%)
|
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|
7015X20 |
7015X25 |
7015X35 |
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|||
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Test |
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|
Symbol |
Parameter |
Condition |
Version |
|
Typ.(2) |
Max. |
Typ.(2) |
Max. |
Typ.(2) |
Max. |
Unit |
ICC |
Dynamic Operating |
CE = VIL, Outputs Open |
MIL. |
S |
— |
— |
155 |
340 |
150 |
300 |
mA |
|
Current |
SEM = VIH |
|
L |
— |
— |
155 |
280 |
150 |
250 |
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f = fMAX(3) |
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(Both Ports Active) |
COM’L. |
S |
160 |
290 |
155 |
265 |
150 |
250 |
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L |
160 |
240 |
155 |
220 |
150 |
210 |
|
ISB1 |
Standby Current |
CEL = CER = VIH |
MIL. |
S |
— |
— |
16 |
80 |
13 |
80 |
mA |
|
(Both Ports — TTL |
SEMR = SEML = VIH |
|
L |
— |
— |
16 |
65 |
13 |
65 |
|
|
|
f = fMAX(3) |
|
|
|
|
|
|
|
|
|
|
Level Inputs) |
COM’L. |
S |
20 |
60 |
16 |
60 |
13 |
60 |
|
|
|
|
|
|
L |
20 |
50 |
16 |
50 |
13 |
50 |
|
ISB2 |
Standby Current |
CE"A"=VIL and CE"B"=VIH(5) |
MIL. |
S |
— |
— |
90 |
215 |
85 |
190 |
mA |
|
(One Port — TTL |
Active Port Outputs Open |
|
L |
— |
— |
90 |
180 |
85 |
160 |
|
|
Level Inputs) |
f = fMAX(3) |
|
|
|
|
|
|
|
|
|
|
COM’L. |
S |
95 |
180 |
90 |
170 |
85 |
155 |
|
||
|
|
SEMR = SEML = VIH |
|
L |
95 |
150 |
90 |
140 |
85 |
130 |
|
ISB3 |
Full Standby Current |
Both Ports CEL and |
MIL. |
S |
— |
— |
1.0 |
30 |
1.0 |
30 |
mA |
|
(Both Ports — All |
CER > VCC - 0.2V |
|
L |
— |
— |
0.2 |
10 |
0.2 |
10 |
|
|
CMOS Level Inputs) |
VIN > VCC - 0.2V or |
COM’L. |
S |
1.0 |
15 |
1.0 |
15 |
1.0 |
15 |
|
|
|
VIN < 0.2V, f = 0(4) |
|
L |
0.2 |
5 |
0.2 |
5 |
0.2 |
5 |
|
|
|
SEMR = SEML > VCC - 0.2V |
|
|
|
|
|
|
|
|
|
ISB4 |
Full Standby Current |
CE"A"< 0.2V and |
MIL. |
S |
— |
— |
85 |
200 |
80 |
175 |
mA |
|
(One Port — All |
CE"B" > VCC - 0.2V(5) |
|
L |
— |
— |
85 |
170 |
80 |
150 |
|
|
CMOS Level Inputs) |
SEMR = SEML > VCC - 0.2V |
|
|
|
|
|
|
|
|
|
|
|
VIN > VCC - 0.2V or |
COM’L. |
S |
90 |
155 |
85 |
145 |
80 |
135 |
|
|
|
VIN < 0.2V |
|
L |
90 |
130 |
85 |
120 |
80 |
110 |
|
|
|
Active Port Outputs Open, |
|
|
|
|
|
|
|
|
|
|
|
f = fMAX(3) |
|
|
|
|
|
|
|
|
|
NOTES: |
|
|
|
|
|
|
|
|
|
2954 tbl 10 |
|
1."X" in part numbers indicates power rating (S or L).
2.VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA(typ.)
3.At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4.f = 0 means no address or control lines change.
5.Port "A" may be either left or right port. Port "B" is the opposite of port "A".
OUTPUT LOADS AND AC TEST CONDITIONS
Input Pulse Levels |
GND to 3.0V |
Input Rise/Fall Times(1) |
5ns Max. |
Input Timing Reference Levels |
1.5V |
Output Reference Levels |
1.5V |
Output Load |
Figure 1 and 2 |
|
|
NOTE: |
|
1. 3ns Max. for tAA=12ns |
|
|
5V |
|
5V |
|
893Ω |
|
893Ω |
DATAOUT |
|
|
|
BUSY |
|
DATAOUT |
|
INT |
|
|
|
|
|
|
|
347Ω |
30pF |
347Ω |
5pF* |
|
2954 drw 05 |
|
2954 drw 06 |
Figure 1. AC Output Test Load |
Figure 2. Output Test Load |
||
|
|
(For tLZ, tHZ, tWZ, tOW) |
|
|
|
Including scope and jig. |
|
6.12 |
6 |
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