Integrated Device Technology Inc IDT71321LA20J, IDT71321LA20PF, IDT71321LA25J, IDT71321LA25PF, IDT71321LA25TF Datasheet

HIGH-SPEED 2K x 8

IDT71321SA/LA

DUAL-PORT STATIC RAM

IDT71421SA/LA

WITH INTERRUPTS

Integrated Device Technology, Inc.

FEATURES:

•High-speed access

—Commercial: 20/25/35/45/55ns (max.)

•Low-power operation —IDT71321/IDT71421SA

Active: 550mW (typ.) Standby: 5mW (typ.)

—IDT71321/421LA Active: 550mW (typ.) Standby: 1mW (typ.)

•Two INT flags for port-to-port communications

•MASTER IDT71321 easily expands data bus width to 16- or-more-bits using SLAVE IDT71421

•On-chip port arbitration logic (IDT71321 only)

•BUSY output flag on IDT71321; BUSY input on IDT71421

•Fully asynchronous operation from either port

•Battery backup operation —2V data retention (LA Only)

•TTL-compatible, single 5V ±10% power supply

•Available in popular hermetic and plastic packages

•Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications

DESCRIPTION:

The IDT71321/IDT71421 are high-speed 2K x 8 DualPort Static RAMs with internal interrupt logic for interprocessor communications. The IDT71321 is designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the IDT71421 "SLAVE" DualPort in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-or-more- bit memory system applications results in full speed, errorfree operation without the need for additional discrete logic.

Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode.

Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 550mW of power. Low-power (LA) versions offer battery backup data retention capability, with each Dual-Port typically consuming 200μW from a 2V battery.

The IDT71321/IDT71421 devices are packaged in a 52pin PLCC, a 64-pin TQFP, and a 64-pin STQFP.

FUNCTIONAL BLOCK DIAGRAM

OEL

CEL

R/WL

I/O0L- I/O7L

(1,2)

BUSYL

A10L

A0L

NOTES:

1.IDT71321 (MASTER): BUSY

is open drain output and requires pullup resistor of 270Ω.

IDT71421 (SLAVE): BUSY is input.

2.Open drain output: requires pullup resistor of 270Ω.

(2)

INTL

OER

CER

R/WR

I/O		I/O	I/O0R-I/O7R
Control		Control
			(1,2)
			BUSYR
Address	MEMORY	Address	A10R
Decoder	ARRAY	Decoder	A0R
11		11
	ARBITRATION
CEL	and	CER
	INTERRUPT
OEL		OER
	LOGIC
R/WL
		R/WR
			(2)
			INTR
			2691 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE	OCTOBER 1996
©1996 Integrated Device Technology, Inc. For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.	DSC-2691/6

6.03	1

IDT71321SA/LA AND IDT71421SA/LA

HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

PIN CONFIGURATIONS (1,2)

A0L

OE

A10L

INT

BUSYL

R/W

CE

VCC

CE

R/WR

R

INT

A10R

BUSY

NDEX

L

L

L

L

R

R

A1L

87

6

5

4

3

2

52 51 50 49 48 47

OER

1

A2L

46

A 0R

9

45

A3L

10

44

A 1R

A4L

11

43

A 2R

A5L

12

42

A 3R

A6L

13

IDT71321/421

41

A 4R

A7L

14

J52-1

40

A 5R

PLCC

A8L

15

TOP VIEW (3)

39

A 6R

A9L

16

38

A 7R

I/O 0L

17

37

A 8R

I/O 1L

18

36

A 9R

I/O 2L

19

35

NC

I/O 3L

20

34

I/O7R

21 22 23 24 25 26 27 28 29 30 31 32 33

4L

5L

6L

7L

NC

GND

0R

1R

2R

3R

4R

5R

6R

2691 drw 02

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

NOTES:

1.All Vcc pins must be connected to the power supply.

2.All GND pins must be connected to the ground supply.

3.This text does not indicate orientation of the actual part-marking.

COMMERCIAL TEMPERATURE RANGE

					N/C		N/C		A10L		INTL		BUSYL R/WL				CEL		VCC		VCC		RCE R/W				BUSYR		INTR		A10R		N/C		N/C
																										R
INDEX
					64		63		62		61		60		59		58		57		56		55		54		53		52		51		50		49
OEL					1																																48		OER
A0L					2																																47		A 0R
A1L					3																																46		A 1R
A2L					4																																45		A 2R
A3L					5												IDT71321/421																				44		A 3R
A4L					6																																43		A 4R
															PN64-1 / PP64-1
A5L					7												64-PIN TQFP																				42		A 5R
A6L					8																																41		A 6R
N/C					9											64-PIN STQFP																					40		N/C
																	TOP VIEW (3)
A7L					10																																39		A 7R
A8L					11																																38		A 8R
A9L					12																																37		A 9R
N/C					13																																36		N/C
I/O 0L					14																																35		N/C
I/O 1L					15		18		19		20		21		22		23		24		25				27		28		29		30		31				34		I/O7R
I/O 2L					1617																		26												32		33		I/O6R
																																						2691 drw 03
					I/O 3L		N/C		4L		5L			6L		7L	N/C		GND		GND			0R		1R		2R		3R	N/C			4R		5R
									I/O		I/O		I/O		I/O								I/O		I/O		I/O		I/O				I/O		I/O

ABSOLUTE MAXIMUM RATINGS(1)

Symbol	Rating	Commercial		Unit
VTERM(2)	Terminal Voltage	–0.5 to +7.0		V
	with Respect to
	GND
TA	Operating	0 to +70		°C
	Temperature
TBIAS	Temperature	–55 to +125		°C
	Under Bias
TSTG	Storage	–55 to +125		°C
	Temperature
IOUT	DC Output	50		mA
	Current
NOTES:			2691 tbl 01

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.5V.

RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE

	Ambient
Grade	Temperature	GND	VCC
Commercial	0°C to +70°C	0V	5.0V ± 10%

2691 tbl 02

RECOMMENDED

DC OPERATING CONDITIONS

Symbol	Parameter	Min.	Typ.	Max.		Unit
VCC	Supply Voltage	4.5	5.0	5.5		V
GND	Supply Voltage	0	0	0		V
VIH	Input High Voltage	2.2	—	6.0(2)		V
VIL	Input Low Voltage	–0.5(1)	—	0.8		V
NOTES:					2691 tbl 03

1.VIL (min.) = -1.5V for pulse width less than 10ns.

2.VTERM must not exceed Vcc + 0.5V.

CAPACITANCE(1,3)

(TA = +25°C, f = 1.0MHz) TQFP ONLY

Symbol	Parameter	Conditions(2)	Max.		Unit
CIN	Input Capacitance	VIN = 3dV	9		pF
COUT	Output Capacitance	VIN = 3dV	10		pF
NOTES:				2691 tbl 04

1.This parameter is determined by device characterization but is not production tested.

2.3dv references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.

3.11pF max. for other packages.

6.03

2

IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS	COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,4) (VCC = 5.0V ± 10%)

					71321X20		71321X25		71321X35		71321X55		71321X100
							71421X25		71421X35		71421X55		71421X100
Symbol	Parameter	Test Conditions	Version		Typ. Max.		Typ. Max.		Typ. Max.		Typ. Max.		Typ. Max.		Unit
ICC	Dynamic Operating	CEL and CER = VIL,	MIL.	SA	—	—	110	280	80	230	65	190	65	190	mA
	Current (Both Ports	Outputs open,		LA	—	—	110	220	80	170	65	140	65	140
	Active)	f = fMAX(2)	COM'L. SA		110	250	110	220	80	165	65	155	65	155
				LA	110	200	110	170	80	120	65	110	65	110
ISB1	Standby Current	CEL and CER = VIH,	MIL.	SA	—	—	30	80	25	80	20	65	20	65	mA
	(Both Ports - TTL	f = fMAX(2)		LA	—	—	30	60	25	60	20	45	20	45
	Level Inputs)		COM'L. SA		30	65	30	65	25	65	20	65	20	55
				LA	30	45	30	45	25	45	20	35	20	35
ISB2	Standby Current	CE"A" = VIL and	MIL.	SA	—	—	65	160	50	150	40	125	40	125	mA
	(One Port - TTL	CE"B" = VIH (5)		LA	—	—	65	125	50	115	40	90	40	90
	Level Inputs)	Active Port Outputs	COM'L. SA		65	165	65	150	50	125	40	110	40	110
		Open, f = fMAX(2)		LA	65	125	65	115	50	90	40	75	40	75
ISB3	Full Standby Current	CEL and	MIL.	SA	—	—	1.0	30	1.0	30	1.0	30	1.0	30	mA
	(Both Ports - All	CER > VCC -0.2V,		LA	—	—	0.2	10	0.2	10	0.2	10	0.2	10
	CMOS Level Inputs	VIN > VCC -0.2V or	COM'L. SA		1.0	15	1.0	15	1.0	15	1.0	15	1.0	15
		VIN < 0.2V,f = 0(3)		LA	0.2	5	0.2	5	0.2	4	0.2	4	0.2	4
ISB4	Full Standby Current	CE"A" < 0.2V and	MIL.	SA	—	—	60	155	45	145	40	110	40	110	mA
	(One Port - All	CE"B" > VCC -0.2V(5)		LA	—	—	60	115	45	105	40	85	40	80
	CMOS Level Inputs)	VIN > VCC -0.2V or	COM'L. SA		60	155	60	145	45	110	40	100	40	95
		VIN < 0.2V,		LA	60	115	60	105	45	85	40	70	40	70
		Active Port Outputs
		Open, f = fMAX(2)
NOTES:														2689 tbl 05

1.'X' in part numbers indicates power rating (SA or LA).

2.At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input levels of GND to 3V.

3.f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

4.Vcc = 5V, TA=+25°C for Typ. and is not production tested. Vcc DC = 100mA (Typ)

5.Port "A" may be either left or right port. Port "B" is opposite from port "A".

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)

				IDT71321SA		lDT71321LA
				IDT71421SA		lDT71421LA
Symbol		Parameter	Test Conditions	Min.	Max.	Min.	Max.	Unit
|lLl|		Input Leakage	VCC = 5.5V,	—	10	—	5	μA
		Current(1)	VIN = 0V to VCC
|lLO|		Output Leakage	CE = VIH, VOUT = 0V to VCC	—	10	—	5	μA
		Current(1)	VCC = 5.5V
VOL		Output Low Voltage	lOL = 4mA	—	0.4	—	0.4	V
		(l/O0-l/O7)
VOL		Open Drain Output Low	lOL = 16mA	—	0.5	—	0.5	V
		Voltage (BUSY,INT)
VOH		Output High Voltage	lOH = -4mA	2.4	—	2.4	—	V
NOTE: 1.	At Vcc < 2.0V leakages are undefined.							2691 tbl 06

6.03

3

IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS	COMMERCIAL TEMPERATURE RANGE

DATA RETENTION CHARACTERISTICS (LA Version Only)

						71321LA/71421LA
Symbol	Parameter	Test Conditions			Min.	Typ.(1)	Max.	Unit
VDR	VCC for Data Retention				2.0	—	0	V
ICCDR	Data Retention Current	VCC = 2.0V, CE > VCC - 0.2V	COM'L.		—	100	1500	μA
tCDR(3)	Chip Deselect to Data	VIN > VCC - 0.2V or VIN≤ 0.2V			0	—	—	ns
	Retention Time
tR(3)	Operation Recovery				tRC(2)	—	—	ns
	Time
NOTES:								2691 tbl 07

1.VCC = 2V, TA = +25°C, and is not production tested.

2.tRC = Read Cycle Time

3.This parameter is guaranteed by device characterization but not production tested.

	DATA RETENTION WAVEFORM				AC TEST CONDITIONS
		DATA RETENTION MODE			Input Pulse Levels	GND to 3.0V
					Input Rise/Fall Times	5ns
					Input Timing Reference Levels	1.5V
	VCC	4.5V	VDR ³ 2.0V	4.5V	Output Reference Levels	1.5V
					Output Load	Figures 1, 2, and 3
		tCDR		tR		2691 tbl 08
	CE		VDR
		VIH		VIH
				2691 drw 04
			5V		5V
				1250Ω		1250Ω
		DATA OUT			DATA OUT
			775Ω
				30pF	775Ω	5pF
				100pF for 55 and 100ns versions
			Figure 1. AC Output Test Load		Figure 2. Output Test Load
					(for tHZ, tLZ, tWZ, and tOW)
					* Including scope and jig.

5V

270Ω

2691 drw 05

BUSY or INT

30pF

100pF for 55 and 100ns versions

Figure 3. BUSY and INT

AC Output Test Load

6.03

4