Integrated Device Technology Inc IDT7005L15PF, IDT7005L17F, IDT7005L17G, IDT7005L17J, IDT7005L17PF Datasheet

HIGH-SPEED	IDT7005S/L
8K x 8 DUAL-PORT
STATIC RAM

Integrated Device Technology, Inc.

FEATURES:

•True Dual-Ported memory cells which allow simultaneous access of the same memory location

•High-speed access

—Military: 20/25/35/55/70ns (max.)

—Commercial:15/17/20/25/35/55ns (max.)

•Low-power operation

—IDT7005S

Active: 750mW (typ.) Standby: 5mW (typ.)

—IDT7005L

Active: 750mW (typ.) Standby: 1mW (typ.)

•IDT7005 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device

•M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave

•Busy and Interrupt Flags

•On-chip port arbitration logic

•Full on-chip hardware support of Semaphore signaling between ports

•Fully asynchronous operation from either port

•Devices are capable of withstanding greater than 2001V electrostatic discharge

•Battery backup operation—2V data retention

•TTL-compatible, single 5V (±10%) power supply

•Available in 68-pin PGA, 68-pin quad flatpack, 68-pin PLCC, and a 64-pin TQFP

•Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications

DESCRIPTION:

The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM. The IDT7005 is designed to be used as a stand-alone DualPort RAM or as a combination MASTER/SLAVE Dual-Port

FUNCTIONAL BLOCK DIAGRAM

OEL

CEL

R/WL

I/O0L- I/O7L

(1,2)

BUSYL

A12L

A0L

NOTES:

1.	(MASTER):
	BUSY is output;
	(SLAVE): BUSY
	is input.
2.	BUSY outputs
	and INT outputs	SEML
	are non-tri-stated	(2)
		INTL

push-pull.

I/O

I/O

Control

Control

	Address	MEMORY	Address
	Decoder	ARRAY	Decoder
		13	13
		ARBITRATION
	CEL	INTERRUPT	CER
	OEL	SEMAPHORE	OER
		LOGIC
	R/WL		R/WR

M/S

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

OER

CER

R/WR

I/O0R-I/O7R

(1,2)

BUSYR

A12R

A0R

SEMR

(2)

INTR

2738 drw 01

MILITARY AND COMMERCIAL TEMPERATURE RANGES		OCTOBER 1996
©1996 Integrated Device Technology, Inc.	For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.	DSC-2738/6

1

6.06

IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM	MILITARY AND COMMERCIAL TEMPERATURE RANGES

RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic.

This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technol-

ogy, these devices typically operate on only 750mW of power. Low-power (L) versions offer battery backup data retention capability with typical power consumption of 500μW from a 2V battery.

The IDT7005 is packaged in a ceramic 68-pin PGA, a 68pin quad flatpack, a 68-pin PLCC and a 64-pin Thin Plastic Quad Flatpack (TQFP). Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.

PIN CONFIGURATIONS (1,2)

INDEX				I/O1L			I/O0L			N/C OEL						R/WL			SEM L			CEL			N/C			N/C			VCC A12L						A11L			A10L			A9L			A8L A7L						A6L
I/O2L		9				8			7					6		5			4			3			2			1			68 67 66 65 64															63 62 61											A5L
		10																																																		60
I/O3L		11																																																		59					A4L
I/O4L		12																																																		58					A3L
I/O5L		13																																																		57					A2L
GND		14																						IDT7005																												56					A1L
I/O6L		15																																																		55					A0L
																									J68-1
I/O7L		16																							F68-1																											54					INTL
VCC		17																																																		53					BUSYL
GND		18																PLCC / FLATPACK																																		52					GND
I/O0R		19																			TOP VIEW (3)																															51					M/S
I/O1R		20																																																		50					BUSYR
I/O2R		21																																																		49					INTR
VCC		22																																																		48					A0R
I/O3R		23																																																		47					A1R
I/O4R		24																																																		46					A2R
I/O5R		25																																																		45					A3R
I/O6R		26																																																		44					A4R
		27				28 29						30 31							32 33 34 35												36 37 38 39												40 41 42 43
		I/O7R N/C ROE R/WR												SEMR CER N/C N/C GND																	A12R A11R						A10R			A9R			A8R A7R A6R									A5R			2738 drw 02

INDEX

I/O2L

I/O3L

I/O4L

I/O5L

GND

I/O6L

I/O7L

VCC

GND

I/O0R

I/O1R

I/O2R

VCC

I/O3R

I/O4R

I/O5R

NOTES:

1.All Vcc pins must be connected to the power supply.

2.All GND pins must be connected to the ground supply.

3.This text does not indicate orientation of the the actual part-marking.

	I/O1L
1	64
2
3
4
5
6

7

8

9

10

11

12

13

14

15
16	17
I/O6R

I/O0L		OEL		R/WL		SEML
63		62		61		60

18	19		20		21
I/O7R	ROE		R/WR		SEMR

CEL		N/C		VCC		A12L		A11L		A10L
59		58		57		56		55		54

IDT7005

PN-64

TQFP

TOP VIEW (3)

22		23		24		25		26		27
CER		N/C		GND			A12R		A11R		A10R

A9L		A8L		A7L		A6L		A5L
53		52		51		50		49		48
										47
										46
										45
										44
										43
										42
										41
										40
										39
										38
										37
										36
										35
										34
28		29		30		31		32		33
	A9R		A8R		A7R		A6R		A5R

A4L

A3L

A2L

A1L

A0L

INTL

BUSYL

GND

M/S

BUSYR

INTR

A0R

A1R

A2R

A3R

A4R

2738 drw 03

6.06

2

IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM	MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS (CON'T.)(1,2)

	11			51	50	48	46	44	42	40	38	36
				A5L	A4L	A2L	A0L	BUSYL	M/S	INTR	A1R	A3R
	10	53		52	49	47	45	43	41	39	37	35		34
		A7L		A6L	A3L	A1L	INTL	GND	BUSYR	A0R	A2R	A4R		A5R
	09	55		54								32		33
		A9L		A8L								A7R		A6R
	08	57		56								30		31
		A11L		A10L								A9R		A8R
	07	59		58								28		29
		VCC		A12L				IDT7005				A11R		A10R
								G68-1
	06	61		60								26		27
		N/C		N/C			68-PIN PGA					GND		A12R
							TOP VIEW(3)
	05	63		62								24		25
		SEML		CEL								N/C		N/C
	04	65		64								22		23
		OE	L	R/WL								SEMR		CE	R
	03	67		66								20		21
		I/O0L		N/C								OE	R	R/WR
	02	68		1	3	5	7	9	11	13	15	18		19
		I/O1L		I/O2L	I/O4L	GND	I/O7L	GND	I/O1R	VCC	I/O4R	I/O7R		N/C
	01			2	4	6	8	10	12	14	16	17
				I/O3L	I/O5L	I/O6L	VCC	I/O0R	I/O2R	I/O3R	I/O5R	I/O6R
		A		B	C	D	E	F	G	H	J	K		L

INDEX

2738 drw 04

NOTES:

1.All VCC pins must be connected to power supply.

2.All GND pins must be connected to ground supply.

3.This text does not indicate oriention of the actual part-marking

PIN NAMES

Left Port		Right Port	Names
CEL		CER	Chip Enable
R/WL		R/WR	Read/Write Enable
OEL		OER	Output Enable
A0L – A12L		A0R – A12R	Address
I/O0L – I/O7L		I/O0R – I/O7R	Data Input/Output
SEML		SEMR	Semaphore Enable
INTL		INTR	Interrupt Flag
BUSYL		BUSYR	Busy Flag
	M/S		Master or Slave Select
	VCC		Power
	GND		Ground
			2738 tbl 01

6.06

3

IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM	MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL

	Inputs(1)					Outputs
CE	R/W	OE	SEM			I/O0-7	Mode
H	X	X	H			High-Z	Deselected: Power-Down
L	L	X	H			DATAIN	Write to Memory
L	H	L	H			DATAOUT	Read Memory
X	X	H	X			High-Z	Outputs Disabled
NOTE:							2738 tbl 02
1. A0L — A12L is not equal to A0R — A12R.
							(1)
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL
	Inputs					Outputs
CE	R/W	OE	SEM			I/O0-7	Mode
H	H	L	L			DATAOUT	Read in Semaphore Flag Data 0ut
H	u	X	L			DATAIN	Write I/O0 into Semaphore Flag
L	X	X	L			—	Not Allowed
NOTE:							2738 tbl 03

1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O15. These eight semaphores are addressed by A0 - A2.

ABSOLUTE MAXIMUM RATINGS(1)

Symbol	Rating	Commercial	Military	Unit
VTERM(2)	Terminal Voltage	–0.5 to +7.0	–0.5 to +7.0	V
	with Respect
	to GND
TA	Operating	0 to +70	–55 to +125	°C
	Temperature
TBIAS	Temperature	–55 to +125	–65 to +135	°C
	Under Bias
TSTG	Storage	–55 to +125	–65 to +150	°C
	Temperature
IOUT	DC Output	50	50	mA
	Current
NOTES:			2738 tbl 04

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or 10% maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.5V.

RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE

	Ambient
Grade	Temperature	GND	VCC
Military	–55°C to +125°C	0V	5.0V ± 10%
Commercial	0°C to +70°C	0V	5.0V ± 10%

2738 tbl 05

RECOMMENDED DC OPERATING

CONDITIONS

Symbol	Parameter	Min.	Typ.	Max.	Unit
VCC	Supply Voltage	4.5	5.0	5.5	V
GND	Supply Voltage	0	0	0	V
VIH	Input High Voltage	2.2	—	6.0(2)	V
VIL	Input Low Voltage	–0.5(1)	—	0.8	V
NOTES:				2738 tbl 06

1.VIL > -1.5V for pulse width less than 10ns.

2.VTERM must not exceed Vcc + 0.5V.

CAPACITANCE(1)

(TA = +25°C, f = 1.0MHz) TQFP PACKAGE

Symbol	Parameter	Conditions(2)	Max.		Unit
CIN	Input Capacitance	VIN = 3dV	9		pF
COUT	Output	VOUT = 3dV	10		pF
	Capacitance
NOTES:				2738 tbl 07

1.This parameter is determined by device characterization but is not production tested.

2.3dv references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.

6.06

4

IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM	MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)

			IDT7005S		IDT7005L
Symbol	Parameter	Test Conditions	Min.	Max.	Min.	Max.	Unit
|ILI|	Input Leakage Current(1)	VCC = 5.5V, VIN = 0V to VCC	—	10	—	5	μA
|ILO|	Output Leakage Current	CE = VIH, VOUT = 0V to VCC	—	10	—	5	μA
VOL	Output Low Voltage	IOL = 4mA	—	0.4	—	0.4	V
VOH	Output High Voltage	IOH = -4mA	2.4	—	2.4	—	V
NOTE:							2738 tbl 08

1. At Vcc < 2.0V input leakages are undefined.

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)								(VCC = 5.0V ± 10%)
		Test			7005X15		7005X17		7005X20			7005X25
					Com'l. Only		Com'l. Only
Symbol	Parameter	Condition	Version		Typ.(2) Max.		Typ.(2)	Max.	Typ.(2)		Max.	Typ.(2)	Max.	Unit
ICC	Dynamic Operating	CE = VIL, Outputs Open	MIL.	S	—	—	—	—	160		370	155	340	mA
	Current	SEM = VIH		L	—	—	—	—	150		320	145	280
	(Both Ports Active)	f = fMAX(3)	COM.	S	170	310	170	310	160		290	155	265
				L	160	260	160	260	150		240	145	220
ISB1	Standby Current	CEL = CER = VIH	MIL.	S	—	—	—	—	20		90	16	80	mA
	(Both Ports — TTL	SEMR = SEML = VIH		L	—	—	—	—	10		70	10	65
	Level Inputs	f = fMAX(3)	COM.	S	20	60	20	60	20		60	16	60
				L	10	60	10	50	10		50	10	50
ISB2	Standby Current	CE"A"=VIL and CE"B"=VIH(5)	MIL.	S	—	—	—	—	95		240	90	215	mA
	(One Port — TTL	Active Port Outputs Open		L	—	—	—	—	85		210	80	180
	Level Inputs)	f = fMAX(3)	COM.	S	105	190	105	190	95		180	90	170
		SEMR = SEML > VIH		L	95	160	95	160	85		150	80	140
ISB3	Full Standby Current	Both Ports CEL and	MIL.	S	—	—	—	—	1.0		30	1.0	30	mA
	(Both Ports — All	CER > VCC - 0.2V(5)		L	—	—	—	—	0.2		10	0.2	10
	CMOS Level Inputs)	VIN > VCC - 0.2V or	COM.	S	1.0	15	1.0	15	1.0		15	1.0	15
		VIN < 0.2V, f = 0(4)		L	0.2	5	0.2	5	0.2		5	0.2	5
		SEMR = SEML > VCC - 0.2V
ISB4	Full Standby Current	CE"B" < 0.2V and	MIL.	S	—	—	—	—	90		225	85	200	mA
	(One Port — All	CE"B" > VCC - 0.2v
	CMOS Level Inputs)	SEMR = SEML > VCC - 0.2V		L	—	—	—	—	80		200	75	170
		VIN > VCC - 0.2V or	COM.	S	100	170	100	170	90		155	85	145
		VIN < 0.2V
		Active Port Outputs Open,		L	90	140	90	140	80		130	75	120
		f = fMAX(3)
NOTES:													2738 tbl 09

1."X" in part numbers indicates power rating (S or L).

2.VCC = 5V, TA = +25°C, and are not production tested. ICC DC = 120mA typ.)

3.At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.

4.f = 0 means no address or control lines change.

5.Port "A"may be either left or right port. Port "B" is the port opposite port "A".

6.06

5

IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM	MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Cont'd.) (VCC = 5.0V ± 10%)

					7005X35		7005X55		7005X70
		Test							Mil. Only
Symbol	Parameter	Condition	Version		Typ.(2)	Max.	Typ.(2)	Max.	Typ.(2)	Max.	Unit
ICC	Dynamic Operating	CE = VIL, Outputs Open	MIL.	S	150	300	150	300	140	300	mA
	Current	SEM = VIH		L	140	250	140	250	130	250
		f = fMAX(3)
	(Both Ports Active)		COM’L.	S	150	250	150	250	—	—
				L	140	210	140	210	—	—
ISB1	Standby Current	CEL = CER = VIH	MIL.	S	13	80	13	80	10	80	mA
	(Both Ports — TTL	SEMR = SEML = VIH		L	10	65	10	65	10	65
		f = fMAX(3)
	Level Inputs)		COM’L.	S	13	60	13	60	—	—
				L	10	50	10	50	—	—
ISB2	Standby Current	CE"A"=VIL and CE"B"=VIL(5)	MIL.	S	85	190	85	190	80	190	mA
	(One Port — TTL	Active Port Outputs Open		L	75	160	75	160	70	160
	Level Inputs)	f = fMAX(3)
			COM’L.	S	85	155	85	155	—	—
		SEMR = SEML = VIH		L	75	130	75	130	—	—
ISB3	Full Standby Current	Both Ports CEL and	MIL.	S	1.0	30	1.0	30	1.0	30	mA
	(Both Ports — All	CER > VCC - 0.2V		L	0.2	10	0.2	10	0.2	10
	CMOS Level Inputs)	VIN > VCC - 0.2V or	COM’L.	S	1.0	15	1.0	15	—	—
		VIN < 0.2V, f = 0(4)		L	0.2	5	0.2	5	—	—
		SEMR = SEML > VCC - 0.2V
ISB4	Full Standby Current	One Port CE"A" < 0.2V	MIL.	S	80	175	80	175	75	175	mA
	(One Port — All	CE"B" > VCC - 0.2V(5)
	CMOS Level Inputs)	SEMR = SEML > VCC - 0.2V		L	70	150	70	150	65	150
		VIN > VCC - 0.2V or	COM’L.	S	80	135	80	135	—	—
		VIN < 0.2V
		Active Port Outputs Open,		L	70	110	80	110	—	—
		f = fMAX(3)
NOTES:										2738 tbl 10

1."X" in part numbers indicates power rating (S or L).

2.VCC = 5V, TA = +25°C and are not production tested. ICC DC = 120mA (typ.)

3.At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.

4.f = 0 means no address or control lines change.

5.Port "A" may be either left or right port. Port "B" is the port opposite port "A".

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)

(VLC = 0.2V, VHC = VCC - 0.2V)(4)

Symbol	Parameter	Test Condition		Min.	Typ.(1)	Max.	Unit
VDR	VCC for Data Retention	VCC = 2V		2.0	—	—	V
ICCDR	Data Retention Current	CE > VHC	MIL.	—	100	4000	μA
		VIN > VHC or ≤ VLC	COM’L.	—	100	1500
tCDR(3)	Chip Deselect to Data Retention Time	SEM > VHC		0	—	—	ns
tR(3)	Operation Recovery Time			tRC(2)	—	—	ns
NOTES:							2738 tbl 11

1.TA = +25°C, VCC = 2V, and are not production tested.

2.tRC = Read Cycle Time

3.This parameter is guaranteed by device characteriation, but is not production tested.

DATA RETENTION WAVEFORM
		DATA RETENTION MODE
VCC	4.5V	VDR ³ 2V	4.5V
	tCDR		tR
CE	VIH	VDR	VIH
			2738 drw 05

6.06

6