Integrated Device Technology Inc IDT54FCT162260CTPAB, IDT54FCT162260CTPF, IDT54FCT162260CTPFB, IDT54FCT162260CTPV, IDT54FCT162260CTPVB Datasheet

								FAST CMOS	IDT54/74FCT16260AT/CT/ET
								12-BIT TRI-PORT	IDT54/74FCT162260AT/CT/ET
								BUS EXCHANGER
Integrated Device Technology, Inc.

FEATURES:

•Common features:

–0.5 MICRON CMOS Technology

–High-speed, low-power CMOS replacement for ABT functions

–Typical tSK(o) (Output Skew) < 250ps

–Low input and output leakage ≤1μA (max.)

–ESD > 2000V per MIL-STD-883, Method 3015;

>200V using machine model (C = 200pF, R = 0)

–Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack

–Extended commercial range of -40°C to +85°C

–VCC = 5V ±10%

•Features for FCT16260AT/CT/ET:

–High drive outputs (-32mA IOH, 64mA IOL)

–Power off disable outputs permit “live insertion”

–Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C

•Features for FCT162260AT/CT/ET:

–Balanced Output Drivers: ±24mA (commercial),

±16mA (military)

–Reduced system switching noise

–Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,TA = 25°C

DESCRIPTION:

The FCT16260AT/CT/ET and the FCT162260AT/CT/ET Tri-Port Bus Exchangers are high-speed 12-bit latched bus multiplexers/transceivers for use in high-speed microprocessor applications. These Bus Exchangers support memory interleaving with latched outputs on the B ports and address multiplexing with latched inputs on the B ports.

The Tri-Port Bus Exchanger has three 12-bit ports. Data may be transferred between the A port and either/both of the B ports. The latch enable (LE1B, LE2B, LEA1B and LEA2B) inputs control data storage. When a latch-enable input is HIGH, the latch is transparent. When a latch-enable input is LOW, the data at the input is latched and remains latched until the latch enable input is returned HIGH. Independent output enables (OE1B and OE2B) allow reading from one port while writing to the other port.

The FCT16260AT/CT/ET are ideally suited for driving high capacitance loads and low impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers.

The FCT162260AT/CT/ET have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times - reducing the need for external series terminating resistors.

FUNCTIONAL BLOCK DIAGRAM

	OE1B
	LEA1B	A-1B	1B1:12
		LATCH	12
	LE1B	1B-A
	12	LATCH	12
	SEL	12
	OEA
	A1:12	M 1
		U
	12	X 0
	12	12
		2B-A
	LE2B	LATCH	12
		A-2B	2B1:12
	LEA2B	LATCH
			12
	OE2B

The IDT logo is a registered trademark of Integrated Device Technology, Inc.		3032 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES		AUGUST 1996
©1996 Integrated Device Technology, Inc.	5.4	DSC-3032/6

1

IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER	MILITARY AND COMMERCIAL TEMPERATURES RANGES

PIN CONFIGURATIONS

OEA		1		56		OE2B
LE1B		2		55		LEA2B
2B3		3		54		2B4
GND		4		53		GND
2B2		5		52		2B5
2B1		6		51		2B6
VCC		7		50		VCC
A1		8		49		2B7
A2		9		48		2B8
A3		10		47		2B9
GND		11		46		GND
A4		12		45		2B10
A5		13		44		2B11
A6		14	SO56-1	43		2B12
A7		15	SO56-2
			SO56-3	42		1B12
A8		16		41		1B11
A9		17		40		1B10
GND		18		39		GND
A10		19		38		1B9
A11		20		37		1B8
A12		21		36		1B7
VCC		22		35		VCC
1B1		23		34		1B6
1B2		24		33		1B5
GND		25		32		GND
1B3		26		31		1B4
LE2B		27		30		LEA1B
SEL		28		29		OE1B

	SSOP/	3032 drw 02
	TSSOP/TVSOP
	TOP VIEW

OEA		1	56		OE2B
LE1B		2	55		LEA2B
2B3		3	54		2B4
GND		4	53		GND
2B2		5	52		2B5
2B1		6	51		2B6
VCC		7	50		VCC
A1		8	49		2B7
A2		9	48		2B8
A3		10	47		2B9
GND		11	46		GND
A4		12	45		2B10
A5		13	44		2B11
A6		14	E56-1 43		2B12
A7		15	42		1B12
A8		16	41		1B11
A9		17	40		1B10
GND		18	39		GND
A10		19	38		1B9
A11		20	37		1B8
A12		21	36		1B7
VCC		22	35		VCC
1B1		23	34		1B6
1B2		24	33		1B5
GND		25	32		GND
1B3		26	31		1B4
LE2B		27	30		LEA1B
SEL		28	29		OE1B
			CERPACK		3032 drw 03
			TOP VIEW

5.4

2

3032 tbl 05

IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER	MILITARY AND COMMERCIAL TEMPERATURES RANGES

PIN DESCRIPTION

Signal	I/O		Description
A(1:12)	I/O	Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
1B(1:12)	I/O	Bidirectional Data Port 1B.	Connected to the even path or even bank of memory.
2B(1:12)	I/O	Bidirectional Data Port 2B.	Connected to the odd path or odd bank of memory.
LEA1B	I	Latch Enable Input for A-1B Latch. The Latch is open when LEA1B is HIGH. Data from the A-port is latched on
		the HIGH to LOW transition of LEA1B.
LEA2B	I	Latch Enable Input for A-2B Latch. The Latch is open when LEA2B is HIGH. Data from the A-Port is latched on
		the HIGH to LOW transition of LEA2B.
LE1B	I	Latch Enable Input for the 1B-A Latch. The Latch is open when LE1B is HIGH. Data from the 1B port is latched
		on the HIGH to LOW transition of LE1B.
LE2B	I	Latch Enable Input for the 2B-A Latch. The Latch is open when LE2B is HIGH. Data from the 2B port is latched
		on the HIGH to LOW transition of LE2B.
SEL	I	1B or 2B Path Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables
		data transfer from 2B Port to A Port.
OEA	I	Output Enable for A Port (Active LOW).
OE1B	I	Output Enable for 1B Port (Active LOW).
OE2B	I	Output Enable for 2B Port (Active LOW).

ABSOLUTE MAXIMUM RATINGS(1)

Symbol	Description	Max.	Unit
VTERM(2)	Terminal Voltage with Respect to	–0.5 to +7.0	V
	GND
VTERM(3)	Terminal Voltage with Respect to	–0.5 to	V
	GND	VCC +0.5
TSTG	Storage Temperature	–65 to +150	°C
IOUT	DC Output Current	–60 to +120	mA
NOTES:		3032 tbl 02

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.All device terminals except FCT162XXXT Output and I/O terminals.

3.Output and I/O terminals for FCT162XXXT.

CAPACITANCE (TA = +25°C, F = 1.0MHZ)

Symbol	Parameter(1)	Conditions	Typ.	Max.	Unit
CIN	Input	VIN = 0V	3.5	6.0	pF
	Capacitance
CI/O	I/O	VOUT = 0V	3.5	8.0	pF
	Capacitance
NOTE:				3032 tbl 03

1. This parameter is measured at characterization but not tested.

FUNCTION TABLES(2)						3032 tbl 01
		Inputs				Output
1B	2B	SEL	LE1B	LE2B	OEA	A
H	X	H	H	X	L	H
L	X	H	H	X	L	L
X	X	H	L	X	L	A(1)
X	H	L	X	H	L	H
X	L	L	X	H	L	L
X	X	L	X	L	L	A(1)
X	X	X	X	X	H	Z
						3032 tbl 04
		Inputs			Outputs
A	LEA1B LEA2B OE1B			OE2B	1B	2B
H	H	H	L	L	H	H
L	H	H	L	L	L	L
H	H	L	L	L	H	B(1)
L	H	L	L	L	L	B(1)
H	L	H	L	L	B(1)	H
L	L	H	L	L	B(1)	L
X	L	L	L	L	B(1)	B(1)
X	X	X	H	H	Z	Z
X	X	X	L	H	Active	Z
X	X	X	H	L	Z	Active
X	X	X	L	L	Active	Active

NOTES:

1.Output level before the indicated steady-state input conditions were established.

2.H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care

Z = High Impedance

− = LOW-to-HIGH Transition

5.4

3