Integrated Device Technology Inc. IDT54FCT374, IDT54FCT374A, IDT54FCT374C, IDT74FCT374, IDT74FCT374A User Manual

IDT70V07L

HIGH-SPEED 3.3V	IDT70V07S/L
32K x 8 DUAL-PORT
STATIC RAM

Integrated Device Technology, Inc.

FEATURES:

•True Dual-Ported memory cells which allow simultaneous access of the same memory location

•High-speed access

—Commercial: 25/35/55ns (max.)

•Low-power operation

—IDT70V07S

Active: 450mW (typ.) Standby: 5mW (typ.)

—IDT70V07L

Active: 450mW (typ.) Standby: 5mW (typ.)

•IDT70V07 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device

•M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave

•Busy and Interrupt Flags

•On-chip port arbitration logic

•Full on-chip hardware support of semaphore signaling between ports

•Fully asynchronous operation from either port

•Devices are capable of withstanding greater than 2001V electrostatic discharge

•LVTTL-compatible, single 3.3V (±0.3V) power supply

•Available in 68-pin PGA, 68-pin PLCC, and a 64-pin TQFP

DESCRIPTION:

The IDT70V07 is a high-speed 32K x 8 Dual-Port Static RAM. The IDT70V07 is designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE DualPort RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic.

FUNCTIONAL BLOCK DIAGRAM

OEL	OER
CEL	CER
R/WL	R/WR

I/O0L- I/O7L				I/O0R-I/O7R
	I/O		I/O
	Control		Control
(1,2)				(1,2)
BUSYL
				BUSYR
A14L	Address	MEMORY	Address	A14R
A0L	Decoder	ARRAY	Decoder	A0R
	15		15
		ARBITRATION
	CEL	INTERRUPT	CER
	OEL	SEMAPHORE	OER
		LOGIC
	R/WL		R/WR
SEML		M/S		SEMR
(2)				(2)
INTL				INTR
				2943 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
COMMERCIAL TEMPERATURE RANGE				OCTOBER 1996
©1996 Integrated Device Technology, Inc.	For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.			DSC-2943/3

6.37

1

IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM	COMMERCIAL TEMPERATURE RANGE

This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 450mW of power.

The IDT70V07 is packaged in a ceramic 68-pin PGA, a 68pin PLCC, and a 80-pin thin plastic quad flatpack (TQFP).

PIN CONFIGURATIONS (1,2)

INDEX

A6L

A7L

A8L

A9L

A10L

A11L

A12L

VCC

A13L

A14L

CEL

SEM L

R/WL

OEL

N/C

I/O0L

I/O1L

9 I/O2L 10 I/O3L 11

I/O4L 12 I/O5L 13

GND 14

I/O6L 15 I/O7L 16 VCC 17

GND 18

I/O0R 19 I/O1R 20 I/O2R 21 VCC 22 I/O3R 23 I/O4R 24 I/O5R 25

I/O6R 26 27

I/O7R

8	7	6	5	4	3	2	1	68 67 66 65 64 63 62 61		A5L
									60
									59	A4L
									58	A3L
									57	A2L
									56	A1L
					IDT70V07				55	A0L
						J68-1			54	INTL

PLCC	53			BUSYL
	52			GND
TOP	51			M/S
VIEW(3)	50			BUSYR
	49			INTR
	48			A0R
	47			A1R
	46			A2R
	45			A3R
	44			A4R
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43						1LI/O			I/O0L N/C LOE R/LW LSEM LCE N/C A14L A13L VCC A12L																							A11L A10L A9L A8L 7LA											A6L N/C
N/C ROE R/WR SEMR CER A14R A13R GND A12R A11R A10R A9R A8R A7R	A6R A5R
		2943 drw 02
	INDEX
	N/C				1	80			79 78 77 76 75 74 73 72 71 70 69																							68 67 66 65 64 63 62
	I/O2L				2
	I/O3L				3
	I/O4L				4
	I/O5L				5
	GND				6
	I/O6L				7																				70V07
	I/O7L				8																				PN80-1
	VCC				9
	N/C				10																				TQFP
	GND				11																					TOP
	I/O0R				12																			VIEW(3)
	I/O1R				13
	I/O2R				14
	VCC				15
	I/O3R				16
	I/O4R				17
	I/O5R				18
	I/O6R				19
	N/C				20				22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37																																		38 39
					21

N/C
61			N/C
60
59			A5L
58			A4L
57			A3L
56			A2L
55			A1L
54			A0L
53			INTL
52			BUSYL
51			GND
50			M/S
49			BUSYR
48			INTR
47			A0R
46			A1R
45			A2R
44			A3R
43			A4R
42			N/C
41			N/C
40

2943 drw 03

NOTES:

1.All Vcc pins must be connected to the power supply.

2.All GND pins must be connected to the ground supply.

3.This text does not indicate the actual part marking.

N/C

N/C

A5R

A6R

A7R

A8R

A9R

A10R

A11R

A12R

GND

A13R

A14R

N/C

CER

SEMR

R/WR

OER

N/C

I/O7R

6.37

2

IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM											COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CONT'D) (1,2)
11		51	50	48	46	44	42		40	38	36
		A5L	A4L	A2L	A0L	BUSYL	M/S		INTR	A1R	A3R
10	53	52	49	47	45	43	41		39	37	35	34
	A7L	A6L	A3L	A1L	INTL	GND	BUSYR		A0R	A2R	A4R	A5R
09	55	54									32	33
	A9L	A8L									A7R	A6R
08	57	56									30	31
	A11L	A10L									A9R	A8R
07	59	58			IDT70V07						28	29
	VCC	A12L									A11R	A10R
						G68-1
06	61	60									26	27
	A14L	A13L			68-PIN PGA						GND	A12R
					TOP VIEW(3)
05	63	62									24	25
	SEML	CEL									A14R	A13R
04	65	64									22	23
	OE	R/WL									SEMR	CE	R
	L
03	67	66									20	21
	I/O0L	N/C									OER	R/WR
02	68	1	3	5	7	9	11		13	15	18	19
	I/O1L	I/O2L	I/O4L	GND	I/O7L	GND	I/O1R		VCC	I/O4R	I/O7R	N/C
01		2	4	6	8	10	12		14	16	17
		I/O3L	I/O5L	I/O6L	VCC	I/O0R	I/O2R		I/O3R	I/O5R	I/O6R
	A	B	C	D	E	F	G		H	J	K	L
INDEX
												2943 drw 04

NOTES:

1.All VCC pins must be connected to power supply.

2.All GND pins must be connected to ground supply.

3.This text does not indicate orientation of the actual part-marking.

PIN NAMES

Left Port		Right Port	Names
CEL		CER	Chip Enable
R/WL		R/WR	Read/Write Enable
OEL		OER	Output Enable
A0L – A14L		A0R – A14R	Address
I/O0L – I/O7L		I/O0R – I/O7R	Data Input/Output
SEML		SEMR	Semaphore Enable
INTL		INTR	Interrupt Flag
BUSYL		BUSYR	Busy Flag
	M/S		Master or Slave Select
	VCC		Power
	GND		Ground
			2943 tbl 01

6.37

3

IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM	COMMERCIAL TEMPERATURE RANGE

TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL

	Inputs(1)			Outputs
CE	R/W	OE	SEM	I/O0-7	Mode
H	X	X	H	High-Z	Deselected: Power-Down
L	L	X	H	DATAIN	Write to Memory
L	H	L	H	DATAOUT	Read Memory
X	X	H	X	High-Z	Outputs Disabled
NOTE:					2943 tbl 02
1. A0L — A14L ¹ A0R — A14R.
					(1)
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL
	Inputs			Outputs
CE	R/W	OE	SEM	I/O0-7	Mode
H	H	L	L	DATAOUT	Read Data in Semaphore Flag
H		X	L	DATAIN	Write I/O0 into Semaphore Flag
L	X	X	L	—	Not Allowed
NOTE:					2943 tbl 03

1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.

ABSOLUTE MAXIMUM RATINGS (1)

Symbol	Rating	Commercial	Unit
VTERM(2)	Terminal Voltage	–0.5 to +4.6	V
	with Respect
	to GND
TA	Operating	0 to +70	°C
	Temperature
TBIAS	Temperature	–55 to +125	°C
	Under Bias
TSTG	Storage	–55 to +125	°C
	Temperature
IOUT	DC Output	50	mA
	Current
NOTES:		2943 tbl 04

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.

RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE

	Ambient
Grade	Temperature	GND	VCC
Commercial	0°C to +70°C	0V	3.3V ± 0.3V

2943 tbl 05

RECOMMENDED DC OPERATING

CONDITIONS (2)

Symbol	Parameter	Min.	Typ.	Max.	Unit
VCC	Supply Voltage	3.0	3.3	3.6	V
GND	Supply Voltage	0	0	0	V
VIH	Input High Voltage	2.0	—	VCC+0.3	V
VIL	Input Low Voltage	–0.3(1)	—	0.8	V
NOTES:				2943 tbl 06

1.VIL > -1.5V for pulse width less than 10ns.

2.VTERM must not exceed Vcc + 0.3V.

CAPACITANCE(1)

(TA = +25°C, f = 1.0MHz)TQFP ONLY

Symbol	Parameter	Conditions(2)	Max.		Unit
CIN	Input Capacitance	VIN = 3dV	9		pF
COUT	Output	VOUT = 3dV	10		pF
	Capacitance
NOTES:				2943 tbl 07

1.This parameter is determined by device characterization but is not production tested.

2.3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.

6.37

4

IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM	COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 3.3V ± 0.3V)

			IDT70V07S		IDT70V07L
Symbol	Parameter	Test Conditions	Min.	Max.	Min.	Max.	Unit
|ILI|	Input Leakage Current(1)	VCC = 3.6V, VIN = 0V to VCC	—	10	—	5	μA
|ILO|	Output Leakage Current	CE = VIH, VOUT = 0V to VCC	—	10	—	5	μA
VOL	Output Low Voltage	IOL = 4mA	—	0.4	—	0.4	V
VOH	Output High Voltage	IOH = -4mA	2.4	—	2.4	—	V
NOTE:							2943 tbl 08

1. At Vcc ≤ 2.0V input leakages are undefined.

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)							(VCC = 3.3V ± 0.3V)
					70V07X25			70V07X35		70V07X55
		Test
Symbol	Parameter	Condition	Version		Typ.(2)		Max.	Typ.(2)	Max.	Typ.(2)	Max.	Unit
ICC	Dynamic Operating	CE = VIL, Outputs Open	COM’L.	S	100		170	90	140	90	140	mA
	Current	SEM = VIH		L	100		140	90	120	90	120
	(Both Ports Active)	f = fMAX(3)
ISB1	Standby Current	CER = CEL = VIH	COM’L.	S	14		30	12	30	12	30	mA
	(Both Ports — TTL	SEMR = SEML = VIH		L	12		24	10	24	10	24
	Level Inputs)	f = fMAX(3)
ISB2	Standby Current	CE"A" = VIL and CE"B" = VIH(5)	COM’L.	S	50		95	45	87	45	87	mA
	(One Port — TTL	Active Port Outputs Open,		L	50		85	45	75	45	75
	Level Inputs)	f = fMAX(3)
		SEMR = SEML = VIH
ISB3	Full Standby Current	Both Ports CEL and	COM’L.	S	1.0		6	1.0	6	1.0	6	mA
	(Both Ports — All	CER > VCC - 0.2V		L	0.2		3	0.2	3	0.2	3
	CMOS Level Inputs)	VIN > VCC - 0.2V or
		VIN < 0.2V, f = 0(4)
		SEMR = SEML > VCC - 0.2V
ISB4	Full Standby Current	CE"A" < 0.2V and	COM’L.	S	60		90	55	85	55	85	mA
	(One Port — All	CE"B" > VCC - 0.2V(5)		L	60		80	55	74	55	74
	CMOS Level Inputs)	SEMR = SEML > VCC - 0.2V
		VIN > VCC - 0.2V or VIN < 0.2V
		Active Port Outputs Open
		f = fMAX(3)
NOTES:											2943 tbl 09

1."X" in part numbers indicates power rating (S or L).

2.VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 80mA (Typ.)

3.At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using “AC Test Conditions” of input levels of GND to 3V.

4.f = 0 means no address or control lines change.

5.Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6.37

5

IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM																		COMMERCIAL TEMPERATURE RANGE
										3.3V																	3.3V
AC TEST CONDITIONS																590Ω																	590Ω
Input Pulse Levels			GND to 3.0V		DATAOUT
Input Rise/Fall Times			5ns Max.			BUSY														DATAOUT
Input Timing Reference Levels			1.5V			INT	435Ω										30pF
																								435Ω										5pF
Output Reference Levels			1.5V
Output Load			Figures 1 and 2
													2943 drw 05																	2943 drw 06
			2943 tbl 10
				Figure 1. AC Output Test Load																Figure 2. Output Test Load
																						(for tLZ, tHZ, tWZ, tOW)
																						* Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
						IDT70V07X25							IDT70V07X35									IDT70V07X55
Symbol	Parameter					Min.		Max.					Min.						Max.			Min.			Max.					Unit
READ CYCLE
tRC	Read Cycle Time					25		—		35									—		55				—								ns
tAA	Address Access Time					—		25									—		35			—			55								ns
tACE	Chip Enable Access Time(3)					—		25									—		35			—			55								ns
tAOE	Output Enable Access Time					—		15									—		20			—			30								ns
tOH	Output Hold from Address Change					3		—		3									—		3				—								ns
tLZ	Output Low-Z Time(1, 2)					3		—		3									—		3				—								ns
tHZ	Output High-Z Time(1, 2)					—		15									—		20			—			25								ns
tPU	Chip Enable to Power Up Time(2)					0		—		0									—		0				—								ns
tPD	Chip Disable to Power Down Time(2)					—		25									—		35			—			50								ns
tSOP	Semaphore Flag Update Pulse (OE or SEM)					15		—		15									—		15				—								ns
tSAA	Semaphore Address Access Time					—		35									—		45			—			65								ns
NOTES:																											2943 tbl 11

1.Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2.This parameter is guaranteed by device characterization, but is not production tested.

3.To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.

4."X" in part numbers indicates power rating (S or L).

TIMING OF POWER-UP POWER-DOWN

CE

ICC

tPU

tPD

50%

50%

ISB

2943 drw 07

6.37

6