HIGH-SPEED |
IDT7007S/L |
32K x 8 DUAL-PORT |
|
STATIC RAM |
|
Integrated Device Technology, Inc.
FEATURES:
•True Dual-Ported memory cells which allow simultaneous access of the same memory location
•High-speed access
—Military: 25/35/55ns (max.)
—Commercial: 20/25/35/55ns (max.)
•Low-power operation
—IDT7007S
Active: 750mW (typ.) Standby: 5mW (typ.)
—IDT7007L
Active: 750mW (typ.) Standby: 1mW (typ.)
•IDT7007 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading
more than one device
•M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave
•Busy and Interrupt Flags
•On-chip port arbitration logic
•Full on-chip hardware support of semaphore signaling between ports
•Fully asynchronous operation from either port
•Devices are capable of withstanding greater than 2001V electrostatic discharge
•TTL-compatible, single 5V (±10%) power supply
•Available in 68-pin PGA, 68-pin PLCC, and a 80-pin TQFP
•Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
OE |
OER |
L |
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CEL |
CER |
R/WL |
R/WR |
I/O0L- I/O7L |
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I/O0R-I/O7R |
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I/O |
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I/O |
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Control |
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Control |
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(1,2) |
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(1,2) |
BUSYL |
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BUSYR |
A14L |
Address |
MEMORY |
Address |
A14R |
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A0L |
Decoder |
ARRAY |
Decoder |
A0R |
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15 |
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15 |
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ARBITRATION |
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CEL |
INTERRUPT |
CER |
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OEL |
SEMAPHORE |
OER |
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LOGIC |
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R/WL |
R/WR |
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SEML |
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SEMR |
(2) |
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INTR(2) |
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INTL |
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M/S |
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NOTES: |
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2940 drw 01 |
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1.(MASTER): BUSY is output; (SLAVE): BUSY is input.
2.BUSY and INT outputs are non-tri-stated push-pull.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
OCTOBER 1996 |
|
©1996 Integrated Device Technology, Inc. |
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391. |
DSC-2940/4 |
6.08 |
1 |
IDT7007S/L |
|
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
DESCRIPTION:
The IDT7007 is a high-speed 32K x 8 Dual-Port Static RAM. The IDT7007 is designed to be used as a stand-alone 256K-bit Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 750mW of power.
The IDT7007 is packaged in a 68-pin pin PGA, a 68-pin PLCC, and a 80-pin TQFP (thin plastic quad flatpack). Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
PIN CONFIGURATIONS(1,2)
INDEX |
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I/O1L |
I/O0L |
N/C OEL |
R/WL SEML |
CEL A14L |
A13L |
VCC |
A12L |
A11L |
A10L |
A9L A8L A7L |
A6L |
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I/O2L |
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9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
68 67 66 65 64 63 62 61 |
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10 |
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60 |
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I/O3L |
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11 |
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59 |
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I/O4L |
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12 |
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58 |
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I/O5L |
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13 |
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57 |
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GND |
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14 |
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56 |
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I/O6L |
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15 |
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IDT7007 |
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55 |
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I/O7L |
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16 |
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54 |
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VCC |
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17 |
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J68-1 |
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53 |
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PLCC |
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GND |
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18 |
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52 |
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TOP VIEW(3) |
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I/O0R |
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19 |
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51 |
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I/O1R |
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20 |
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50 |
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I/O2R |
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21 |
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49 |
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VCC |
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22 |
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48 |
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I/O3R |
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23 |
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47 |
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I/O4R |
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24 |
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I/O5R |
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25 |
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I/O6R |
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26 |
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27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 |
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I/O7R N/C ROE R/WR SEMR CER |
A14R |
A13R |
GND |
A12R |
A11R |
A10R |
A9R |
A8R A7R A6R |
A5R |
NOTES:
1.All Vcc pins must be connected to power supply.
2.All GND pins must be connected to power supply.
3.This text does not indicate orientation of the actual part marking.
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
2940 drw 02
6.08 |
2 |
IDT7007S/L |
|
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
PIN CONFIGURATIONS (CONT'D.) (1,2)
INDEX
N/C
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
N/C
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
N/C
|
I/O1L |
1 |
80 |
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2 |
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3 |
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4 |
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5 |
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6 |
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7 |
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8 |
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9 |
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10
11
12
13
14
15
16
17
18
19
20 21
79 I/O0L 78 N/C 77 OEL 76 R/WL 75 SEM L 74 CEL
22 23 24 25 26 27
N/C A14L |
A13L |
VCC A12L |
A11L A10L A9L A8L A7L A6L |
N/C N/C |
|
73 72 |
71 |
70 69 |
68 67 66 65 64 63 |
62 |
61 |
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60 |
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59 |
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58 |
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57 |
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56 |
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55 |
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54 |
IDT7007 |
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53 |
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52 |
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PN80-1 |
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51 |
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TQFP |
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50 |
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TOP VIEW |
(3) |
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49 |
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48 |
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47 |
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46 |
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45 |
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44 |
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43 |
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42 |
28 29 30 31 32 |
33 34 35 36 37 38 |
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41 |
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39 40 |
N/C
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
N/C
N/C
2940 drw 03
N/C
N/C
A5R
A6R
A7R
A8R
A9R
A10R
A11R
A12R
GND
A13R
A14R
N/C
CER
SEMR
R/WR
OER
N/C
I/O7R
NOTES:
1.All Vcc pins must be connected to power supply.
2.All GND pins must be connected to power supply.
3.This text does not indicate orientation of the actual part marking.
6.08 |
3 |
IDT7007S/L |
|
|
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|
|
|
|
|
|
|
|
|
|
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
|
|
|
|
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
||||||||
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PIN CONFIGURATIONS (CONT'D.) (1,2) |
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11 |
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51 |
50 |
48 |
46 |
44 |
42 |
40 |
38 |
36 |
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A5L |
A4L |
A2L |
A0L |
BUSYL |
M/S |
INTR |
A1R |
A3R |
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10 |
53 |
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52 |
49 |
47 |
45 |
43 |
41 |
39 |
37 |
35 |
34 |
|
A7L |
A6L |
A3L |
A1L |
INTL |
GND |
BUSYR |
A0R |
A2R |
A4R |
A5R |
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09 |
55 |
|
54 |
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32 |
33 |
|
A9L |
A8L |
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A7R |
A6R |
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08 |
57 |
|
56 |
|
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30 |
31 |
|
A11L |
A10L |
|
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A9R |
A8R |
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||
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07 |
59 |
|
58 |
|
|
|
IDT7007 |
|
|
28 |
29 |
|
|
VCC |
A12L |
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|
A11R |
A10R |
|
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|||||||
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G68-1 |
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|
06 |
61 |
|
60 |
|
|
68-PIN PGA |
|
|
26 |
27 |
|
||
A14L |
A13L |
|
|
TOP VIEW(3) |
|
|
GND |
A12R |
|
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05 |
63 |
|
62 |
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24 |
25 |
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|||||
SEML |
CEL |
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A14R |
A13R |
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04 |
65 |
|
64 |
|
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|
22 |
23 |
|
OE |
L |
R/WL |
|
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SEMR |
CE |
|
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R |
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||
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03 |
67 |
|
66 |
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20 |
21 |
|
I/O0L |
N/C |
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|
OER |
R/WR |
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02 |
68 |
|
1 |
3 |
5 |
7 |
9 |
11 |
13 |
15 |
18 |
19 |
|
I/O1L |
I/O2L |
I/O4L |
GND |
I/O7L |
GND |
I/O1R |
VCC |
I/O4R |
I/O7R |
N/C |
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||||||||||||
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01 |
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2 |
4 |
6 |
8 |
10 |
12 |
14 |
16 |
17 |
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|
I/O3L |
I/O5L |
I/O6L |
VCC |
I/O0R |
I/O2R |
I/O3R |
I/O5R |
I/O6R |
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A |
|
B |
C |
D |
E |
F |
G |
H |
J |
K |
L |
|
INDEX |
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2940 drw 04 |
NOTES:
1.All VCC pins must be connected to power supply.
2.All GND pins must be connected to ground supply.
3.This text does not indicate orientation of the actual part marking.
PIN NAMES
Left Port |
|
Right Port |
Names |
CEL |
|
CER |
Chip Enable |
|
|
|
|
R/WL |
|
R/WR |
Read/Write Enable |
|
|
|
|
OEL |
|
OER |
Output Enable |
|
|
|
|
A0L – A14L |
|
A0R – A14R |
Address |
|
|
|
|
I/O0L – I/O7L |
|
I/O0R – I/O7R |
Data Input/Output |
|
|
|
|
SEML |
|
SEMR |
Semaphore Enable |
|
|
|
|
INTL |
|
INTR |
Interrupt Flag |
|
|
|
|
BUSYL |
|
BUSYR |
Busy Flag |
|
|
|
|
|
M/S |
Master or Slave Select |
|
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|
|
|
VCC |
Power |
|
|
|
|
|
|
GND |
Ground |
|
|
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|
2940 tbl 01 |
6.08 |
4 |
IDT7007S/L |
|
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
TRUTH TABLE: NON-CONTENTION READ/WRITE CONTROL
|
Inputs(1) |
|
Outputs |
|
|
CE |
R/W |
OE |
SEM |
I/O0-7 |
Mode |
|
|
|
|
|
|
H |
X |
X |
H |
High-Z |
Deselected: Power-Down |
|
|
|
|
|
|
L |
L |
X |
H |
DATAIN |
Write to Memory |
|
|
|
|
|
|
L |
H |
L |
H |
DATAOUT |
Read Memory |
|
|
|
|
|
|
X |
X |
H |
X |
High-Z |
Outputs Disabled |
|
|
|
|
|
|
NOTE: |
|
|
|
|
2940 tbl 02 |
1. A0L — A14L ¹ A0R — A14R.
TRUTH TABLE: SEMAPHORE READ/WRITE CONTROL(1)
|
Inputs |
|
Outputs |
|
|
CE |
R/W |
OE |
SEM |
I/O0-7 |
Mode |
|
|
|
|
|
|
H |
H |
L |
L |
DATAOUT |
Read Semaphore Flag Data Out (I/O0-I/O7) |
|
|
|
|
|
|
H |
|
X |
L |
DATAIN |
Write I/O0 into Semaphore Flag |
|
|
|
|
|
|
L |
X |
X |
L |
— |
Not Allowed |
|
|
|
|
|
|
NOTE: |
|
|
|
|
2940 tbl 03 |
1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Rating |
Commercial |
Military |
Unit |
|
|
|
|
|
VTERM(2) |
Terminal Voltage |
–0.5 to +7.0 |
–0.5 to +7.0 |
V |
|
with Respect |
|
|
|
|
to GND |
|
|
|
TA |
Operating |
0 to +70 |
–55 to +125 |
°C |
|
Temperature |
|
|
|
TBIAS |
Temperature |
–55 to +125 |
–65 to +135 |
°C |
|
Under Bias |
|
|
|
TSTG |
Storage |
–55 to +125 |
–65 to +150 |
°C |
|
Temperature |
|
|
|
|
|
|
|
|
IOUT |
DC Output |
50 |
50 |
mA |
|
Current |
|
|
|
|
|
|
|
|
NOTES: |
|
|
2940 tbl 04 |
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.5V.
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
|
Ambient |
|
|
Grade |
Temperature |
GND |
VCC |
|
|
|
|
Military |
–55°C to +125°C |
0V |
5.0V ± 10% |
|
|
|
|
Commercial |
0°C to +70°C |
0V |
5.0V ± 10% |
|
|
|
|
2940 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
Symbol |
Parameter |
Min. |
Typ. |
Max. |
Unit |
|
|
|
|
|
|
VCC |
Supply Voltage |
4.5 |
5.0 |
5.5 |
V |
|
|
|
|
|
|
GND |
Supply Voltage |
0 |
0 |
0 |
V |
|
|
|
|
|
|
VIH |
Input High Voltage |
2.2 |
— |
6.0(2) |
V |
VIL |
Input Low Voltage |
–0.5(1) |
— |
0.8 |
V |
NOTES: |
|
|
|
2940 tbl 06 |
1.VIL > -1.5V for pulse width less than 10ns.
2.VTERM must not exceed Vcc + 0.5V.
CAPACITANCE(1)
(TA = +25°C, f = 1.0MHz)TQFP ONLY
Symbol |
Parameter |
Conditions(1) |
Max. |
|
Unit |
CIN |
Input Capacitance |
VIN = 3dV |
9 |
|
pF |
|
|
|
|
|
|
COUT |
Output |
VOUT = 3dV |
10 |
|
pF |
|
Capacitance |
|
|
|
|
|
|
|
|
|
|
NOTES: |
|
|
|
2940 tbl 07 |
1.This parameter is determined by device characterization but is not production tested.
2.3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
6.08 |
5 |
IDT7007S/L |
|
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
|
|
|
IDT7007S |
IDT7007L |
|
||
Symbol |
Parameter |
Test Conditions |
Min. |
Max. |
Min. |
Max. |
Unit |
|
|
|
|
|
|
|
|
|ILI| |
Input Leakage Current(1) |
VCC = 5.5V, VIN = 0V to VCC |
— |
10 |
— |
5 |
mA |
|ILO| |
Output Leakage Current |
CE = VIH, VOUT = 0V to VCC |
— |
10 |
— |
5 |
mA |
VOL |
Output Low Voltage |
IOL = 4mA |
— |
0.4 |
— |
0.4 |
V |
VOH |
Output High Voltage |
IOH = – 4mA |
2.4 |
— |
2.4 |
— |
V |
|
|
|
|
|
|
|
|
NOTE: |
2940 tbl 08 |
1. At Vcc < 2.0V, input leakages are undefined. |
|
DC ELECTRICAL CHARACTERISTICS OVER THE |
|
|
|
|
|
|
|
||
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) |
(VCC = 5.0V ± 10%) |
|
|
|
|||||
|
|
|
|
|
7007X20 |
7007X25 |
|
||
|
|
Test |
|
|
Com'l. Only |
|
|
|
|
Symbol |
Parameter |
Condition |
Version |
|
Typ.(2) |
Max. |
Typ.(2) |
Max. |
Unit |
ICC |
Dynamic Operating |
CE = VIL, Outputs Open |
MIL. |
S |
— |
— |
170 |
345 |
mA |
|
Current |
SEM = VIH |
|
L |
— |
— |
170 |
305 |
|
|
(Both Ports Active) |
f = fMAX(3) |
COM’L. |
S |
180 |
315 |
170 |
305 |
|
|
|
|
|
L |
180 |
275 |
170 |
265 |
|
ISB1 |
Standby Current |
CER = CEL = VIH |
MIL. |
S |
— |
— |
25 |
100 |
mA |
|
(Both Ports — TTL |
SEMR = SEML = VIH |
|
L |
— |
— |
25 |
80 |
|
|
Level Inputs) |
f = fMAX(3) |
COM’L. |
S |
30 |
85 |
25 |
85 |
|
|
|
|
|
L |
30 |
60 |
25 |
60 |
|
ISB2 |
Standby Current |
CE"A" = VIL and CE"B" = VIH(5) |
MIL. |
S |
— |
— |
105 |
230 |
mA |
|
(One Port — TTL |
Active Port Outputs Open, |
|
L |
— |
— |
105 |
200 |
|
|
Level Inputs) |
f = fMAX(3) |
|
|
|
|
|
|
|
|
COM’L. |
S |
115 |
210 |
105 |
200 |
|
||
|
|
SEMR = SEML = VIH |
|
L |
115 |
180 |
105 |
170 |
|
ISB3 |
Full Standby Current |
Both Ports CEL and |
MIL. |
S |
— |
— |
1.0 |
30 |
mA |
|
(Both Ports — All |
CER > VCC - 0.2V |
|
L |
— |
— |
0.2 |
10 |
|
|
CMOS Level Inputs) |
VIN > VCC - 0.2V or |
COM’L. |
S |
1.0 |
15 |
1.0 |
15 |
|
|
|
VIN < 0.2V, f = 0(4) |
|
L |
0.2 |
5 |
0.2 |
5 |
|
|
|
SEMR = SEML > VCC - 0.2V |
|
|
|
|
|
|
|
ISB4 |
Full Standby Current |
CE"A" < 0.2V and |
MIL. |
S |
— |
— |
100 |
200 |
mA |
|
(One Port — All |
CE"B" > VCC - 0.2V(5) |
|
L |
— |
— |
100 |
175 |
|
|
CMOS Level Inputs) |
SEMR = SEML > VCC - 0.2V |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
VIN ³ VCC - 0.2V or VIN £ 0.2V |
COM’L. |
S |
110 |
185 |
100 |
275 |
|
|
|
Active Port Outputs Open |
|
L |
110 |
160 |
100 |
230 |
|
|
|
f = fMAX(3) |
|
|
|
|
|
|
|
NOTES: |
|
|
|
|
|
|
|
2940 tbl 09 |
1."X" in part numbers indicates power rating (S or L).
2.VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3.At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4.f = 0 means no address or control lines change.
5.Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.08 |
6 |