HIGH-SPEED 3.3V |
IDT70V25S/L |
8K x 16 DUAL-PORT |
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STATIC RAM |
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Integrated Device Technology, Inc.
FEATURES:
•True Dual-Ported memory cells which allow simultaneous access of the same memory location
•High-speed access
—Commercial: 25/35/55ns (max.)
•Low-power operation
—IDT70V25S
Active: 230mW (typ.) Standby: 3.3mW (typ.)
—IDT70V25L
Active: 230mW (typ.) Standby: 0.66mW (typ.)
•Separate upper-byte and lower-byte control for multiplexed bus compatibility
•IDT70V25 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device
•M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave
•Busy and Interrupt Flags
•Devices are capable of withstanding greater than 2001V electrostatic charge.
•On-chip port arbitration logic
•Full on-chip hardware support of semaphore signaling between ports
•Fully asynchronous operation from either port
•LVTTL-compatible, single 3.3V (±0.3V) power supply
•Available in 84-pin PGA, 84-pin PLCC, and 100-pin TQFP
DESCRIPTION:
The IDT70V25 is a high-speed 8K x 16 Dual-Port Static RAM. The IDT70V25 is designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE Dual-
FUNCTIONAL BLOCK DIAGRAM
R/WL |
R/WR |
UBL |
UBR |
LBL |
LBR |
CEL |
CER |
OEL |
OER |
I/O8L-I/O15L |
I/O8R-I/O15R |
I/O |
I/O |
Control |
Control |
I/O0L-I/O7L |
I/O0R-I/O7R |
(1,2)
BUSYL
A12L
A0L
NOTES:
1.(MASTER): BUSY is output; (SLAVE): BUSY is input.
2.BUSY outputs and INT outputs are non-tri-stated push-pull.
SEML
INTL(2)
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BUSYR(1,2) |
Address |
MEMORY |
Address |
A12R |
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Decoder |
ARRAY |
Decoder |
A0R |
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1 3 |
1 3 |
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ARBITRATION |
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CEL |
INTERRUPT |
CER |
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SEMAPHORE |
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OEL |
OER |
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LOGIC |
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R/WL |
R/WR |
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SEMR |
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M/S |
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INTR(2) |
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2944 drw 01 |
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE |
OCTOBER 1996 |
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©1996 Integrated Device Technology, Inc. |
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391. |
DSC-2944/3 |
6.39 |
1 |
IDT70V25S/L |
|
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM |
COMMERCIAL TEMPERATURE RANGE |
Port RAM for 32-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 350mW of power.
The IDT70V25 is packaged in a ceramic 84-pin PGA, an 84-Pin PLCC and a 100-pin Thin Quad Plastic Flatpack.
PIN CONFIGURATIONS (1,2) |
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INDEX |
I/O7L |
I/O6L |
I/O5L |
I/O4L |
I/O3L |
I/O2L |
GND |
I/O1L |
I/O0L |
OEL |
VCC R/WL SEML CEL UBL LBL |
A12L |
A11L |
A10L |
A9L |
A8L |
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I/O8L |
11 10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 84 83 82 81 80 79 78 77 76 75 |
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12 |
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74 |
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A7L |
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I/O9L |
13 |
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73 |
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A6L |
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I/O10L |
14 |
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72 |
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A5L |
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I/O11L |
15 |
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71 |
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A4L |
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I/O12L |
16 |
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70 |
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A3L |
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I/O13L |
17 |
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69 |
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A2L |
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GND |
18 |
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68 |
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A1L |
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I/O14L |
19 |
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67 |
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A0L |
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I/O15L |
20 |
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IDT70V25 |
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66 |
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INTL |
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VCC |
21 |
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J84-1 |
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65 |
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BUSYL |
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GND |
22 |
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84-PIN PLCC |
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64 |
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GND |
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I/O0R |
23 |
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TOP VIEW(3) |
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63 |
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M/S |
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I/O1R |
24 |
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62 |
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BUSY |
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R |
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I/O2R |
25 |
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61 |
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INTR |
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VCC |
26 |
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60 |
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A0R |
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I/O3R |
27 |
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59 |
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A1R |
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I/O4R |
28 |
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58 |
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A2R |
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I/O5R |
29 |
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57 |
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A3R |
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I/O6R |
30 |
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56 |
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A4R |
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I/O7R |
31 |
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55 |
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A5R |
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I/O8R |
32 |
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54 |
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A6R |
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33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 |
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I/O9R |
I/O10R |
I/O11R |
I/O12R |
I/O13R |
I/O14R |
GND |
I/O15R |
OER |
R/WR |
GND SEMR CER UBR LBR A12R |
A11R |
A10R |
A9R |
A8R |
A7R |
2944 drw 02 |
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INDEX |
I/O9L |
I/O8L |
I/O7L |
I/O6L |
I/O5L |
I/O4L |
I/O3L I/O2L GND |
I/O1L |
I/O0L |
OEL VCC R/WL SEML CEL UBL LBL |
A12L |
A11L |
A10L |
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A9L |
A8L |
A7L |
A6L |
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N/C |
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 |
N/C |
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1 |
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75 |
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N/C |
2 |
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74 |
N/C |
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N/C |
3 |
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73 |
N/C |
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N/C |
4 |
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72 |
N/C |
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I/O10L |
5 |
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71 |
A5L |
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I/O11L |
6 |
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70 |
A4L |
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I/O12L |
7 |
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69 |
A3L |
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I/O13L |
8 |
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68 |
A2L |
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GND |
9 |
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67 |
A1L |
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I/O14L |
10 |
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IDT70V25 |
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66 |
A0L |
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I/O15L |
11 |
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65 |
INTL |
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VCC |
12 |
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PN100-1 |
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64 |
BUSYL |
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GND |
13 |
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100-PIN |
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63 |
GND |
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I/O0R |
14 |
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62 |
M/S |
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TQFP |
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I/O1R |
15 |
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TOP VIEW(3) |
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61 |
BUSYR |
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I/O2R |
16 |
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60 |
INTR |
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VCC |
17 |
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59 |
A0R |
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I/O3R |
18 |
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58 |
A1R |
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I/O4R |
19 |
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57 |
A2R |
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I/O5R |
20 |
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56 |
A3R |
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I/O6R |
21 |
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55 |
A4R |
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N/C |
22 |
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54 |
N/C |
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N/C |
23 |
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53 |
N/C |
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N/C |
24 |
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52 |
N/C |
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N/C |
25 |
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51 |
N/C |
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26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 |
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NOTES: |
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I/O7R |
I/O8R |
I/O9R |
I/O10R |
I/O11R |
I/O12R |
I/O13R I/O14R GND |
I/O15R |
ROE |
R/WR GND SEMR CER UBR |
LBR |
A12R |
A11R |
A10R |
A9R |
A8R |
A7R |
A6R |
A5R |
2944 drw 03 |
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1. All Vcc pins must be connected to the power supply. |
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2. All GND pins must be connected to the ground supply. |
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3. This text does not indicate the actual part marking. |
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6.39 |
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2 |
IDT70V25S/L |
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HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM |
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COMMERCIAL TEMPERATURE RANGE |
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PIN CONFIGURATIONS (CONT'D) (1,2) |
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63 |
61 |
60 |
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58 |
55 |
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54 |
51 |
48 |
46 |
45 |
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42 |
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11 |
I/O7L |
I/O5L |
I/O4L |
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I/O2L |
I/O0L |
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OEL |
SEML |
LBL |
A11L |
A10L |
A7L |
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66 |
64 |
62 |
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59 |
56 |
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49 |
50 |
47 |
44 |
43 |
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40 |
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10 |
I/O10L |
I/O8L |
I/O6L |
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I/O3L |
I/O1L |
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UBL |
CEL |
A12L |
A9L |
A8L |
A5L |
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67 |
65 |
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57 |
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53 |
52 |
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41 |
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39 |
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09 |
I/O11L |
I/O9L |
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GND |
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VCC |
R/WL |
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A6L |
A4L |
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69 |
68 |
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38 |
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37 |
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08 |
I/O13L |
I/O12L |
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A3L |
A2L |
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72 |
71 |
73 |
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33 |
35 |
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34 |
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07 |
I/O15L |
I/O14L |
VCC |
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BUSYL |
A0L |
INTL |
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IDT7V025 |
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75 |
70 |
74 |
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32 |
31 |
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36 |
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G84-3 |
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06 |
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I/O0R |
GND |
GND |
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84-PIN PGA |
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GND |
M/S |
A1L |
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TOP VIEW(3) |
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76 |
77 |
78 |
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28 |
29 |
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30 |
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05 |
I/O1R |
I/O2R |
VCC |
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A0R |
INT |
R |
BUSY |
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R |
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79 |
80 |
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26 |
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27 |
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04 |
I/O3R |
I/O4R |
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A2R |
A1R |
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81 |
83 |
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7 |
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11 |
12 |
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23 |
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25 |
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03 |
I/O5R |
I/O7R |
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GND |
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GND |
SEMR |
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A5R |
A3R |
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82 |
1 |
2 |
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5 |
8 |
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10 |
14 |
17 |
20 |
22 |
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24 |
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02 |
I/O6R |
I/O9R |
I/O10R |
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I/O13R |
I/O15R |
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R/WR |
UBR |
A11R |
A8R |
A6R |
A4R |
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84 |
3 |
4 |
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6 |
9 |
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15 |
13 |
16 |
18 |
19 |
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21 |
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01 |
I/O8R |
I/O11R |
I/O12R |
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I/O14R |
OER |
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LBR |
CER |
A12R |
A10R |
A9R |
A7R |
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A |
B |
C |
D |
E |
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F |
G |
H |
J |
K |
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Index |
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2944 drw 04 |
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NOTES:
1.All VCC pins must be connected to power supply.
2.All GND pins must be connected to ground supply.
3.This text does not indicate orientation of the actual partmarking.
PIN NAMES
Left Port |
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Right Port |
Names |
CEL |
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CER |
Chip Enable |
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R/WL |
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R/WR |
Read/Write Enable |
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OEL |
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OER |
Output Enable |
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A0L – A12L |
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A0R – A12R |
Address |
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I/O0L – I/O15L |
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I/O0R – I/O15R |
Data Input/Output |
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SEML |
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SEMR |
Semaphore Enable |
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UBL |
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UBR |
Upper Byte Select |
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LBL |
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LBR |
Lower Byte Select |
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INTL |
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INTR |
Interrupt Flag |
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BUSYL |
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BUSYR |
Busy Flag |
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M/S |
Master or Slave Select |
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VCC |
Power |
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GND |
Ground |
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2944 tbl 01 |
6.39 |
3 |
IDT70V25S/L |
|
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM |
COMMERCIAL TEMPERATURE RANGE |
TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL
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Inputs(1) |
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Outputs |
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CE |
R/W |
OE |
UB |
LB |
SEM |
I/O8-15 |
I/O0-7 |
Mode |
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H |
X |
X |
X |
X |
H |
High-Z |
High-Z |
Deselected: Power Down |
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X |
X |
X |
H |
H |
H |
High-Z |
High-Z |
Both Bytes Deselected |
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L |
L |
X |
L |
H |
H |
DATAIN |
High-Z |
Write to Upper Byte Only |
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L |
L |
X |
H |
L |
H |
High-Z |
DATAIN |
Write to Lower Byte Only |
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L |
L |
X |
L |
L |
H |
DATAIN |
DATAIN |
Write to Both Bytes |
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L |
H |
L |
L |
H |
H |
DATAOUT |
High-Z |
Read Upper Byte Only |
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L |
H |
L |
H |
L |
H |
High-Z |
DATAOUT |
Read Lower Byte Only |
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L |
H |
L |
L |
L |
H |
DATAOUT |
DATAOUT |
Read Both Bytes |
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X |
X |
H |
X |
X |
X |
High-Z |
High-Z |
Outputs Disabled |
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NOTE: |
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2944 tbl 02 |
1. A0L — A12L ¹ A0R — A12R. |
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TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL |
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Inputs |
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Outputs |
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CE |
R/W |
OE |
UB |
LB |
SEM |
I/O8-15 |
I/O0-7 |
Mode |
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H |
H |
L |
X |
X |
L |
DATAOUT |
DATAOUT |
Read Data in Semaphore Flag |
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X |
H |
L |
H |
H |
L |
DATAOUT |
DATAOUT |
Read Data in Semaphore Flag |
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H |
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X |
X |
X |
L |
DATAIN |
DATAIN |
Write DIN0 into Semaphore Flag |
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X |
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X |
H |
H |
L |
DATAIN |
DATAIN |
Write DIN0 into Semaphore Flag |
L |
X |
X |
L |
X |
L |
— |
— |
Not Allowed |
L |
X |
X |
X |
L |
L |
— |
— |
Not Allowed |
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NOTE: |
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2944 tbl 03 |
1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0 - I/O15). These eight semaphores are addressed by A0 - A2.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Rating |
Commercial |
Unit |
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VTERM(2) |
Terminal Voltage |
–0.5 to +4.6 |
V |
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with Respect |
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to GND |
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TA |
Operating |
0 to +70 |
°C |
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Temperature |
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TBIAS |
Temperature |
–55 to +125 |
°C |
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Under Bias |
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TSTG |
Storage |
–55 to +125 |
°C |
|
Temperature |
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IOUT |
DC Output |
50 |
mA |
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Current |
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NOTES: |
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2944 tbl 04 |
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20 mA for the period over VTERM
>Vcc + 0.5V.
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
|
Ambient |
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Grade |
Temperature |
GND |
VCC |
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Commercial |
0°C to +70°C |
0V |
3.3V ± 0.3 |
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2944 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
Symbol |
Parameter |
Min. |
Typ. |
Max. |
Unit |
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VCC |
Supply Voltage |
3.0 |
3.3 |
3.6 |
V |
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GND |
Supply Voltage |
0 |
0 |
0 |
V |
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VIH |
Input High Voltage |
2.0 |
— |
Vcc+0.3 |
V |
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VIL |
Input Low Voltage |
–0.3(1) |
— |
0.8 |
V |
NOTES: |
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2944 tbl 06 |
1.VIL³ -1.5V for pulse width less than 10ns.
2.VTERM must not exceed Vcc + 0.5V.
CAPACITANCE(1)
(TA = +25°C, f = 1.0MHz)TQFP ONLY
Symbol |
Parameter |
Conditions(2) |
Max. |
|
Unit |
CIN |
Input Capacitance |
VIN = 3dV |
9 |
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pF |
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COUT |
Output |
VOUT = 3dV |
10 |
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pF |
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Capacitance |
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NOTES: |
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|
2944 tbl 07 |
1.This parameter is determined by device characterization but is not production tested.
2.3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
6.39 |
4 |
IDT70V25S/L |
|
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM |
COMMERCIAL TEMPERATURE RANGE |
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 3.3V ± 0.3V)
|
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|
IDT70V25S |
IDT70V25L |
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Symbol |
Parameter |
Test Conditions |
Min. |
Max. |
Min. |
Max. |
Unit |
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|ILI| |
Input Leakage Current(1) |
VCC = 3.6V, VIN = 0V to VCC |
— |
10 |
— |
5 |
mA |
|ILO| |
Output Leakage Current |
CE = VIH, VOUT = 0V to VCC |
— |
10 |
— |
5 |
mA |
VOL |
Output Low Voltage |
IOL = 4mA |
— |
0.4 |
— |
0.4 |
V |
VOH |
Output High Voltage |
IOH = -4mA |
2.4 |
— |
2.4 |
— |
V |
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NOTE: |
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|
|
2944 tbl 08 |
1. At Vcc ≤ 2.0V input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 3.3V ± 0.3V)
|
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70V25X25 |
70V25X35 |
70V25X55 |
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|||
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Test |
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Typ.(2) |
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Typ.(2) |
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Typ.(2) |
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Symbol |
Parameter |
Condition |
Version |
|
Max. |
Max. |
Max. |
Unit |
||||
ICC |
Dynamic Operating |
CE = VIL, Outputs Open |
COM’L. |
S |
80 |
170 |
70 |
115 |
70 |
115 |
|
mA |
|
Current |
SEM = VIH |
|
L |
80 |
120 |
70 |
100 |
70 |
100 |
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(Both Ports Active) |
f = fMAX(3) |
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ISB1 |
Standby Current |
CER = CEL = VIH |
COM’L. |
S |
12 |
25 |
10 |
25 |
10 |
25 |
|
mA |
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(Both Ports — TTL |
SEMR = SEML = VIH |
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L |
10 |
20 |
8 |
20 |
8 |
20 |
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Level Inputs) |
f = fMAX(3) |
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ISB2 |
Standby Current |
CEL or CER = VIH(5) |
COM’L. |
S |
40 |
82 |
35 |
72 |
35 |
72 |
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mA |
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(One Port — TTL |
Active Port Outputs Open |
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L |
40 |
72 |
35 |
62 |
35 |
62 |
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Level Inputs) |
f = fMAX(3) |
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SEMR = SEML = VIH |
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ISB3 |
Full Standby Current |
Both Ports CEL and |
COM’L. |
S |
1.0 |
5 |
1.0 |
5 |
1.0 |
5 |
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mA |
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(Both Ports — All |
CER ³ VCC - 0.2V |
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L |
0.2 |
2.5 |
0.2 |
2.5 |
0.2 |
2.5 |
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CMOS Level Inputs) |
VIN ³ VCC - 0.2V or |
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VIN £ 0.2V, f = 0(4) |
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SEMR = SEML ³ VCC - 0.2V |
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ISB4 |
Full Standby Current |
One Port CEL or |
COM’L. |
S |
50 |
81 |
45 |
71 |
45 |
71 |
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mA |
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(One Port — All |
CER ³ VCC - 0.2V(5) |
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L |
50 |
71 |
45 |
61 |
45 |
61 |
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CMOS Level Inputs) |
SEMR = SEML ³ VCC - 0.2V |
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VIN ³ VCC - 0.2V or |
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VIN £ 0.2V |
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Active Port Outputs Open, |
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f = fMAX(3) |
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NOTES: |
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2683 tbl 09 |
1."X" in part numbers indicates power rating (S or L).
2.VCC = 5V, TA = +25°C, and are not production tested. Icc dc = 70mA (typ.)
3.At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4.f = 0 means no address or control lines change.
5.Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.39 |
5 |
IDT70V25S/L |
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HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM |
COMMERCIAL TEMPERATURE RANGE |
AC TEST CONDITIONS |
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3.3V |
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3.3V |
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Input Pulse Levels |
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GND to 3.0V |
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590Ω |
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590Ω |
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Input Rise/Fall Times |
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5ns Max. |
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DATAOUT |
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BUSY |
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Input Timing Reference Levels |
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1.5V |
INT |
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DATAOUT |
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435Ω |
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30pF |
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435Ω |
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5pF |
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Output Reference Levels |
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1.5V |
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Output Load |
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Figures 1 and 2 |
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2944 drw 05 |
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2944 tbl 11 |
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Figure 1. AC Output Load |
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Figure 2. Output Test Load |
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(For tLZ, tHZ, tWZ, tOW) |
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Including scope and jig. |
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AC ELECTRICAL CHARACTERISTICS OVER THE |
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OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4) |
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IDT70V25X25 |
IDT70V25X35 |
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IDT70V25X55 |
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Symbol |
Parameter |
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Min. |
Max. |
Min. |
Max. |
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Min. |
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Max. |
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Unit |
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READ CYCLE |
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tRC |
Read Cycle Time |
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25 |
— |
35 |
— |
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55 |
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— |
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ns |
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tAA |
Address Access Time |
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— |
25 |
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35 |
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ns |
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tACE |
Chip Enable Access Time(3) |
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— |
25 |
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35 |
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55 |
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ns |
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tABE |
Byte Enable Access Time(3) |
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— |
25 |
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35 |
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55 |
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ns |
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tAOE |
Output Enable Access Time |
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15 |
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20 |
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ns |
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tOH |
Output Hold from Address Change |
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3 |
— |
3 |
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3 |
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ns |
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tLZ |
Output Low-Z Time(1, 2) |
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3 |
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3 |
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ns |
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tHZ |
Output High-Z Time(1, 2) |
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15 |
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20 |
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25 |
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ns |
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tPU |
Chip Enable to Power Up Time(2) |
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0 |
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0 |
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ns |
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tPD |
Chip Disable to Power Down Time(2) |
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25 |
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55 |
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ns |
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tSOP |
Semaphore Flag Update Pulse (OE or SEM) |
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15 |
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15 |
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15 |
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ns |
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tSAA |
Semaphore Address Access Time |
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35 |
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45 |
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65 |
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ns |
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NOTES: |
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2944 tbl 12 |
1.Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2.This parameter is guaranteed by device characterization, but is not production tested.
3.To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semephore, CE = VIH or UB & LB = VIH, and SEM = VIL.
4."X" in part numbers indicates power rating (S or L).
TIMING OF POWER-UP POWER-DOWN
CE |
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tPU |
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tPD |
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50% |
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50% |
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ISB |
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2944 drw 06
6.39 |
6 |