Integrated Device Technology Inc IDT70T651S10BC, IDT70T651S10BCI, IDT70T651S10BF, IDT70T651S10BFI, IDT70T651S10DR Datasheet

						HIGH-SPEED 2.5V	PRELIMINARY
						256/128K x 36
							IDT70T651/9S
						ASYNCHRONOUS DUAL-PORT
						STATIC RAM
						WITH 3.3V 0R 2.5V INTERFACE

	Features					Busy and Interrupt Flags
		True Dual-Port memory cells which allow simultaneous				On-chip port arbitration logic
		access of the same memory location				Full on-chip hardware support of semaphore signaling
		High-speed access				between ports
		–	Commercial: 8/10/12/15ns (max.)			Fully asynchronous operation from either port
		–	Industrial: 10/12ns (max.)			Separate byte controls for multiplexed bus and bus
		RapidWrite Mode simplifies high-speed consecutive write				matching compatibility
		cycles				Sleep Mode Inputs on both ports
		Dual chip enables allow for depth expansion without				Supports JTAG features compliant to IEEE 1149.1
		external logic				Single 2.5V (±100mV) power supply for core
		IDT70T651/9 easily expands data bus width to 72 bits or				LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
		more using the Master/Slave select when cascading more				power supply for I/Os and control signals on each port
		than one device				Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad
		M/S = VIH for BUSY output flag on Master,				Flatpack and 208-ball fine pitch Ball Grid Array.
		M/S = VIL for BUSY input on Slave				Industrial temperature range (–40°C to +85°C) is available
						for selected speeds

Functional Block Diagram
BE3L		BE3R
BE2L		BE2R
BE1L		BE1R
BE0L		BE0R
R/WL		R/WR
	B B B B B B B B
	E E E E E E E E
CE0L	0 1 2 3 3 2 1 0	CE0R
CE1L	L L L L R R R R	CE1R

OEL					OER
		Dout0-8_L	Dout0-8_R
		Dout9-17_L	Dout9-17_R
		Dout18-26_L Dout18-26_R
		Dout27-35_L Dout27-35_R
		256/128K x 36
		MEMORY
		ARRAY
I/O0L- I/O35L		Di n_L	Di n_R		I/O0R -I/O35R
(1)	Address			Address	A17R(1)
A17L		ADDR_L	ADDR_R
	Decoder			Decoder	A0R
A0L

CE0L	ARBITRATION
CE1L	INTERRUPT
OEL	SEMAPHORE
R/WL	LOGIC

BUSYL(2,3)
SEML	M/S
INTL(3)

CE0R

CE1R

OER

R/WR

TDI		JTAG		TC K
TD O				TMS
				TRST

BUSYR(2,3)

SEMR

INTR(3)

ZZL(4)			ZZ			ZZR(4)
NOTES:			CONTROL
			LOGIC

1.Address A17x is a NC for IDT70T659.

2.BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

3.	BUSY and	INT are non-tri-state totem-pole outputs (push-pull).	4869 drw 01
4.	The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep
	mode pins	themselves (ZZx) are not affected during sleep mode.	NOVEMBER 2003

1

©2003 IntegratedDevice Technology,Inc.

DSC-5632/3

IDT70T651/9S	Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

Description

The IDT70T651/9 is a high-speed 256/128K x 36 Asynchronous Dual-Port Static RAM. The IDT70T651/9 is designed to be used as a stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic.

This device provides two independent ports with separate control, address,andI/Opinsthatpermitindependent,asynchronousaccessfor reads or writes to any location in memory. An automatic power down

feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.

TheIDT70T651/9hasaRapidWriteModewhichallowsthedesigner to perform back-to-back write operations without pulsing the R/W input each cycle. This is especially significant at the 8 and 10ns cycle times of the IDT70T651/9, easing design considerations at these high performancelevels.

The70T651/9cansupportanoperatingvoltageofeither3.3Vor2.5V on one or both ports, controlled by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.

2

IDT70T651/9S

Preliminary

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Configuration(1,2,3)

70T651/9BC

BC-256(5,6)

256-Pin BGA

03/18/03

Top View

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

NC

TDI

NC

A17L(4)

A14L

A11L

A8L

BE2L

CE1L

OEL

INTL

A5L

A2L

A0L

NC

NC

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

I/O18L

NC

TDO

NC

A15L

A12L

A9L

BE3L

CE0L

R/WL

NC

A4L

A1L

NC

I/O17L

NC

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

I/O18R

I/O19L

VSS

A16L

A13L

A10L

A7L

BE1L

BE0L

SEML

BUSYL

A6L

A3L

OPTL

I/O17R

I/O16L

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

I/O20R I/O19R I/O20L

VDD

VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR

VDD

I/O15R

I/O15L I/O16R

E1

E2

E3

E4

E5

E6

E7

E8

E9

E10

E11

E12

E13

E14

E15

E16

I/O21R I/O21L I/O22L VDDQL

VDD

VDD

VSS

VSS

VSS

VSS

VDD

VDD

VDDQR I/O13L I/O14L I/O14R

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

F11

F12

F13

F14

F15

F16

I/O23L I/O22R I/O23R VDDQL

VDD

NC

VSS

VSS

VSS

VSS

VSS

VDD

VDDQR I/O12R I/O13R I/O12L

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

G13

G14

G15

G16

I/O24R I/O24L

I/O25L VDDQR

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDDQL I/O10L I/O11L I/O11R

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

H12

H13

H14

H15

H16

I/O26L I/O25R I/O26R VDDQR

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDDQL I/O9R

IO9L

I/O10R

J1

J2

J3

J4

J5

J6

J7

J8

J9

J10

J11

J12

J13

J14

J15

J16

I/O27L I/O28R I/O27R VDDQL

ZZR

VSS

VSS

VSS

VSS

VSS

VSS

ZZL

VDDQR

I/O8R

I/O7R

I/O8L

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

K11

K12

K13

K14

K15

K16

I/O29R I/O29L I/O28L VDDQL

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDDQR

I/O6R

I/O6L

I/O7L

L1

L2

L3

L4

L5

L6

L7

L8

L9

L10

L11

L12

L13

L14

L15

L16

I/O30L I/O31R I/O30R VDDQR

VDD

NC

VSS

VSS

VSS

VSS

VSS

VDD

VDDQL

I/O5L

I/O4R

I/O5R

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

M13

M14

M15

M16

I/O32R I/O32L I/O31L VDDQR

VDD

VDD

VSS

VSS

VSS

VSS

VDD

VDD

VDDQL

I/O3R

I/O3L

I/O4L

N1

N2

N3

N4

N5

N6

N7

N8

N9

N10

N11

N12

N13

N14

N15

N16

I/O33L I/O34R I/O33R

VDD

VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL

VDD

I/O2L

I/O1R

I/O2R

P1

P2

P3

P4

P5

P6

P7

P8

P9

P10

P11

P12

P13

P14

P15

P16

I/O35R

I/O34L

TMS

A16R

A13R

A10R

A7R

BE1R

BE0R

SEMR BUSYR

A6R

A3R

I/O0L

I/O0R

I/O1L

,

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

R16

I/O35L

NC

TRST

NC

A15R

A12R

A9R

BE3R

CE0R

R/WR M/S

A4R

A1R

OPTR

NC

NC

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

NC

TCK

NC

A17R(4)

A14R

A11R

A8R

BE2R

CE1R

OER

INTR

A5R

A2R

A0R

NC

NC

5632 drw 02f

NOTES:

,

1.All VDD pins must be connected to 2.5V power supply.

2.All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is set to VSS (0V).

3.All VSS pins must be connected to ground supply.

4.A17X is a NC for IDT70T659.

5.Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

6.This package code is used to reference the package diagram.

3

IDT70T651/9S	Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

Pin Configurations(1,2,3) (con't.)

03/18/03

I/O19L

I/O19R

I/O20L

I/O20R

VDDQL

VSS

I/O21L

I/O21R

I/O22L

I/O22R

VDDQR

VSS

I/O23L

I/O23R

I/O24L

I/O24R

VDDQL

VSS

I/O25L

I/O25R

I/O26L

I/O26R

VDDQR

ZZR

VDD

VDD

VSS

VSS

VDDQL

VSS

I/O27R

I/O27L

I/O28R

I/O28L

VDDQR

VSS

I/O29R

I/O29L

I/O30R

I/O30L

VDDQL

VSS

I/O31R

I/O31L

I/O32R

I/O32L

VDDQR

VSS

I/O33R

I/O33L

I/O34R

I/O34L

	VSS	VDDQR	I/O18R		I/O18L	VSS	VDD	TDI TDO		NC	NC	A17L	A16L	A15L	A14L	A13L	A12L	A11L	A10L	A9L	A8L	A7L	BE3L	BE2L	BE1L	BE0L	CE1L	CE0L	VDD	VDD	VSS	VSS	SEML	OEL	WR/L	BUSYL	INTL	NC	A6L	A5L	A4L	A3L	A2L	A1L	A0L	VDD	VDD	VSS	OPTL	I/O17L		I/O17R	VDDQR	VSS
												(4)
1	208	207	206	205		204	203	202	201	200	199	198	197	196	195	194	193	192	191	190	189	188	187	186	185	184	183	182	181	180	179	178	177	176	175	174	173	172	171	170	169	168	167	166	165	164	163	162	161	160		159	158	157			I/O16L
																																																						156
2																																																						155			I/O16R
3																																																						154			I/O15L
4																																																						153			I/O15R
5																																																						152			VSS
6																																																						151			VDDQL
7																																																						150			I/O14L
8																																																						149			I/O14R
9																																																						148			I/O13L
10																																																						147			I/O13R
11																																																						146			VSS
12																																																						145			VDDQR
13																																																						144			I/O12L
14																																																						143			I/O12R
15																																																						142			I/O11L
16																																																						141			I/O11R
17																																																						140			VSS
18																																																						139			VDDQL
19																																																						138			I/O10L
20																																																						137			I/O10R
21																								70T651/9DR																														136			I/O9L
22																																																						135			I/O9R
23																								DR-208(5,6,7)																														134			VSS
24																																																						133			VDDQR
																																																									VDD
25																																																						132
26																										208-Pin																												131			VDD
																																																									VSS
27																																																						130			VSS
28																										PQFP																												129			ZZL
29																																																						128
																																																									VDDQL
30																								Top View(8)																														127
31																																																						126			I/O8R
																																																									I/O8L
32																																																						125
																																																									I/O7R
33																																																						124
34																																																						123			I/O7L
35																																																						122			VSS
36																																																						121			VDDQR
37																																																						120			I/O6R
38																																																						119			I/O6L
39																																																						118			I/O5R
40																																																						117			I/O5L
41																																																						116			VSS
42																																																						115			VDDQL
43																																																						114			I/O4R
44																																																						113			I/O4L
45																																																						112			I/O3R
46																																																						111			I/O3L
47																																																						110			VSS
48																																																						109			VDDQR
49																																																						108			I/O2R
50																																																						107			I/O2L
51																																																						106			I/O1R
52																																																	100	101		102	103	105			I/O1L
53		54	55	56		57	58	59	60	61	62	63	64	65	66	67	68	69	70	71	72	73	74	75	76	77	78	79	80	81	82	83	84	85	86	87	88	89	90	91	92	93	94	95	96	97	98	99						104
																																																								5632 drw 02d
	VSS	VDDQL	I/O35R	I/O35L		VDD	TMS TCK TRST			NC	NC	A17R	A16R	A15R	A14R	A13R	A12R	A11R	A10R	A9R	A8R	A7R	BE3R	BE2R	BE1R	BE0R	CE1R	CE0R	VDD	VDD	VSS	VSS	SEMR	OER	WR/R	BUSYR	INTR	M/S	A6R	A5R	A4R	A3R	A2R	A1R	A0R	VDD	VSS	VSS	OPTR	I/O0L		I/O0R	VDDQL	VSS
												(4)

NOTES:

1. All VDD pins must be connected to 2.5V power supply.

2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V) and 2.5V if OPT pin for that port is set to VSS (0V).

3.All VSS pins must be connected to ground.

4.A17X is a NC for IDT70T659.

5.Package body is approximately 28mm x 28mm x 3.5mm.

6.This package code is used to reference the package diagram.

7.8ns Commercial and 10ns Industrial speed grades are not available in the DR-208 package.

8.This text does not indicate orientation of the actual part-marking.

4

IDT70T651/9S	Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

Pin Configurations(1,2,3)(con't.)

03/18/03

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

A

I/O19L

I/O18L

VSS

TDO

NC

A16L

A12L

A8L

BE1L

VDD

SEML

INTL

A4L

A0L

OPTL

I/O17L

VSS

B

I/O20R

VSS

I/O18R

TDI

A17L (4)

A13L

A9 L

BE2L

CE0L

VSS

BUSYL

A5L

A1L

VSS

VDDQR

I/O16L

I/O15R

C

VDDQL

I/O19R

VDDQR

VDD

NC

A14 L

A1 0L

BE3L

CE1L

VSS

R/WL

A6L

A2L

VDD

I/O16R

I/O15L

VSS

D

I/O22L

VSS

I/O21L

I/O20L

A15L

A11L

A7 L

BE0L

VDD

OEL

NC

A3L

VDD

I/O17R

VDDQ L

I/O14L

I/O14R

E

I/O23L

I/O22R

VDDQ R

I/O21R

I/O12L

I/O13R

VSS

I/O13L

F

VDDQL

I/O23R

I/O24L

VSS

VSS

I/O12R

I/O11L

VDDQR

G

I/O26L

VSS

I/O25L

I/O24R

I/O9L

VDDQL

I/O10L

I/O11R

70T651/9BF

H

VDD

I/O26R

VDDQR

I/O25R

VDD

I/O9R

VSS

I/O10R

BF-208(5,6)

J

VDDQL

VDD

VSS

ZZR

208-Ball

ZZL

VDD

VSS

VDDQR

K

I/O28R

VSS

I/O27R

VS S

fpBGA

I/O7R

VDDQL

I/O8R

VSS

Top View(7)

L

I/O29R

I/O28L

VDDQ R

I/O27L

I/O6R

I/O7L

VSS

I/O8L

M

VDDQL

I/O29L

I/O30R

VSS

VSS

I/O6L

I/O5R

VDDQR

N

I/O31L

VSS

I/O31R

I/O30L

I/O3R

VDDQL

I/O4R

I/O5L

P

I/O32R

I/O32L

VDDQ R

I/O3 5R

TRST

A16R

A12R

A8R

BE1R

VDD

SEMR

INTR

A4R

I/O2L

I/O3L

VSS

I/O4L

R

VSS

I/O33L

I/O34R

TCK

A17R(4)

A13R

A9R

BE2R

CE0R

VSS

BUSYR

A5 R

A1R

VSS

VDDQ L

I/O1R

VDDQR

T

I/O33R

I/O34L

VDDQL

TMS

NC

A14R

A1 0R

BE3R

CE1R

VSS

R/WR

A6R

A2R

VS S

I/O0R

VSS

I/O2R

U

VSS

I/O35L

VDD

NC

A15R

A11R

A7 R

BE0R

VDD

OER

M/S

A3R

A0R

VDD

OPTR

I/O0L

I/O1L

5632 drw 02e

A B C D E F G H J K L M N P R T U

NOTES:

1. All VDD pins must be connected to 2.5V power supply.

2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V) and 2.5V if OPT pin for that port is set to VSS (0V).

3.All VSS pins must be connected to ground.

4.A17X is a NC for IDT70T659.

5.Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

6.This package code is used to reference the package diagram.

7.This text does not indicate orientation of the actual part-marking.

5

IDT70T651/9S	Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

Pin Names

Left Port		Right Port	Names
CE0L, CE1L		CE0R, CE1R	Chip Enables (Input)
R/WL		R/WR	Read/Write Enable (Input)
OEL		OER	Output Enable (Input)
A0L - A17L(1)		A0R - A17R(1)	Address (Input)
I/O0L - I/O35L		I/O0R - I/O35R	Data Input/Output
SEML		SEMR	Semaphore Enable (Input)
INTL		INTR	Interrupt Flag (Output)
BUSYL		BUSYR	Busy Flag (Output)
BE0L - BE3L		BE0R - BE3R	Byte Enables (9-bit bytes) (Input)
VDDQL		VDDQR	Power (I/O Bus) (3.3V or 2.5V)(2) (Input)
OPTL		OPTR	Option for selecting VDDQX(2,3) (Input)
ZZL		ZZR	Sleep Mode Pin(4) (Input)
	M/S		Master or Slave Select (Input)(5)
	VDD		Power (2.5V)(2) (Input)
	VSS		Ground (0V) (Input)
	TDI		Test Data Input
	TDO		Test Data Output
	TCK		Test Logic Clock (10MHz) (Input)
	TMS		Test Mode Select (Input)
	TRST		Reset (Initialize TAP Controller) (Input)
			5632 tbl 01

NOTES:

1.Address A17x is a NC for IDT70T659.

2.VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on I/OX.

3.OPTX selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V.

4.The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected during sleep mode. It is recommended that boundry scan not be operated during sleep mode.

5.BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

6

IDT70T651/9S

Preliminary

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Truth Table I—Read/Write and Enable Control(1,2)

Byte 3

Byte 2

Byte 1

Byte 0

OE

SEM

CE0

CE1

BE3

BE2

BE1

BE0

R/W

ZZ

I/O27-35

I/O18-26

I/O9-17

I/O0-8

MODE

X

H

H

X

X

X

X

X

X

L

High-Z

High-Z

High-Z

High-Z

Deselected–Power Down

X

H

X

L

X

X

X

X

X

L

High-Z

High-Z

High-Z

High-Z

Deselected–Power Down

X

H

L

H

H

H

H

H

X

L

High-Z

High-Z

High-Z

High-Z

All Bytes Deselected

X

H

L

H

H

H

H

L

L

L

High-Z

High-Z

High-Z

DIN

Write to Byte 0 Only

X

H

L

H

H

H

L

H

L

L

High-Z

High-Z

DIN

High-Z

Write to Byte 1 Only

X

H

L

H

H

L

H

H

L

L

High-Z

DIN

High-Z

High-Z

Write to Byte 2 Only

X

H

L

H

L

H

H

H

L

L

DIN

High-Z

High-Z

High-Z

Write to Byte 3 Only

X

H

L

H

H

H

L

L

L

L

High-Z

High-Z

DIN

DIN

Write to Lower 2 Bytes Only

X

H

L

H

L

L

H

H

L

L

DIN

DIN

High-Z

High-Z

Write to Upper 2 bytes Only

X

H

L

H

L

L

L

L

L

L

DIN

DIN

DIN

DIN

Write to All Bytes

L

H

L

H

H

H

H

L

H

L

High-Z

High-Z

High-Z

DOUT

Read Byte 0 Only

L

H

L

H

H

H

L

H

H

L

High-Z

High-Z

DOUT

High-Z

Read Byte 1 Only

L

H

L

H

H

L

H

H

H

L

High-Z

DOUT

High-Z

High-Z

Read Byte 2 Only

L

H

L

H

L

H

H

H

H

L

DOUT

High-Z

High-Z

High-Z

Read Byte 3 Only

L

H

L

H

H

H

L

L

H

L

High-Z

High-Z

DOUT

DOUT

Read Lower 2 Bytes Only

L

H

L

H

L

L

H

H

H

L

DOUT

DOUT

High-Z

High-Z

Read Upper 2 Bytes Only

L

H

L

H

L

L

L

L

H

L

DOUT

DOUT

DOUT

DOUT

Read All Bytes

H

H

L

H

L

L

L

L

X

L

High-Z

High-Z

High-Z

High-Z

Outputs Disabled

X

X

X

X

X

X

X

X

X

H

High-Z

High-Z

High-Z

High-Z

High-Z Sleep Mode

NOTES:

5632 tbl 02

1."H" = VIH, "L" = VIL, "X" = Don't Care.

2.It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table II – Semaphore Read/Write Control(1)

			Inputs(1)					Outputs
CE(2)	R/W	OE	BE3	BE2	BE1	BE0	SEM	I/O1-35	I/O0	Mode
H	H	L	L	L	L	L	L	DATAOUT	DATAOUT	Read Data in Semaphore Flag(3)
H	↑	X	X	X	X	L	L	X	DATAIN	Write I/O0 into Semaphore Flag
L	X	X	X	X	X	X	L	______	______	Not Allowed

NOTES:	5632 tbl 03

1.There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O35). These eight semaphore flags are addressed by A0-A2.

2.CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.

3.Each byte is controlled by the respective BEn. To read data BEn = VIL.

7

IDT70T651/9S	Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

RecommendedOperating

Temperature and Supply Voltage(1)

	Ambient
Grade	Temperature	GND	VDD
Commercial	0OC to +70OC	0V	2.5V + 100mV
Industrial	-40OC to +85OC	0V	2.5V + 100mV

NOTE:	5632 tbl 04

1. This is the parameter TA. This is the "instant on" case temperature.

Capacitance(1)

(TA = +25°C, F = 1.0MHZ) PQFP ONLY

Symbol	Parameter	Conditions(2)	Max.	Unit
CIN	Input Capacitance	VIN = 3dV	8	pF
COUT(3)	Output Capacitance	VOUT = 3dV	10.5	pF

NOTES:	5632 tbl 08

1.These parameters are determined by device characterization, but are not production tested.

2.3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V.

3.COUT also references CI/O.

Recommended DC Operating Conditions with VDDQ at 2.5V

Symbol	Parameter	Min.	Typ.	Max.		Unit
VDD	Core Supply Voltage	2.4	2.5	2.6		V
VDDQ	I/O Supply Voltage(3)	2.4	2.5	2.6		V
VSS	Ground	0	0	0		V
	Input High Volltage	1.7		VDDQ + 100mV(2)		V
VIH	(Address, Control &		____
	Data I/O Inputs)(3)
VIH	Input High Voltage _	1.7	____	VDD + 100mV(2)		V
	JTAG
VIH	Input High Voltage -	VDD - 0.2V	____	VDD + 100mV(2)		V
	ZZ, OPT, M/S
VIL	Input Low Voltage	-0.3(1)	____	0.7		V
VIL	Input Low Voltage -	-0.3(1)	____	0.2		V
	ZZ, OPT, M/S
					5632 tbl 05

NOTES:

1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.

2.VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is less.

3.To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VSS(0V), and VDDQX for that port must be supplied as indicated above.

Absolute Maximum Ratings(1)

Symbol	Rating	Commercial	Unit
		& Industrial
VTERM	VDD Terminal Voltage	-0.5 to 3.6	V
(VDD)	with Respect to GND
VTERM(2)	VDDQ Terminal Voltage	-0.3 to VDDQ + 0.3	V
(VDDQ)	with Respect to GND
VTERM(2)	Input and I/O Terminal	-0.3 to VDDQ + 0.3	V
(INPUTS and I/O's)	Voltage with Respect to GND
TBIAS(3)	Temperature	-55 to +125	oC
	Under Bias
TSTG	Storage	-65 to +150	oC
	Temperature
TJN	Junction Temperature	+150	oC
IOUT(For VDDQ = 3.3V)	DC Output Current	50	mA
IOUT(For VDDQ = 2.5V)	DC Output Current	40	mA

5632 tbl 07

NOTES:

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed VDDQ during power supply ramp up.

3.Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.

Recommended DC Operating Conditions with VDDQ at 3.3V

	Symbol	Parameter	Min.	Typ.	Max.	Unit
	VDD	Core Supply Voltage	2.4	2.5	2.6	V
	VDDQ	I/O Supply Voltage(3)	3.15	3.3	3.45	V
	VSS	Ground	0	0	0	V
		Input High Voltage			VDDQ + 150mV(2)
	VIH	(Address, Control	2.0	____		V
		&Data I/O Inputs)(3)
	VIH	Input High Voltage _	1.7	____	VDD + 100mV(2)	V
		JTAG
	VIH	Input High Voltage -	VDD - 0.2V	____	VDD + 100mV(2)	V
		ZZ, OPT, M/S
	VIL	Input Low Voltage	-0.3(1)	____	0.8	V
	VIL	Input Low Voltage -	-0.3(1)	____	0.2	V
		ZZ, OPT, M/S
					5632 tbl 06

NOTES:

1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.

2.VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is less.

3.To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied as indicated above.

8

IDT70T651/9S	Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)

			70T651/9S
Symbol	Parameter	Test Conditions	Min.	Max.	Unit
|ILI|	Input Leakage Current(1)	VDDQ = Max., VIN = 0V to VDDQ	___	10	µA
|ILI|	JTAG & ZZ Input Leakage Current(1,2)	VDD = Max., VIN = 0V to VDD	___	+30	µA
|ILO|	Output Leakage Current(1,3)	CE0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ	___	10	µA
VOL (3.3V)	Output Low Voltage(1)	IOL = +4mA, VDDQ = Min.	___	0.4	V
VOH (3.3V)	Output High Voltage(1)	IOH = -4mA, VDDQ = Min.	2.4	___	V
VOL (2.5V)	Output Low Voltage(1)	IOL = +2mA, VDDQ = Min.	___	0.4	V
VOH (2.5V)	Output High Voltage(1)	IOH = -2mA, VDDQ = Min.	2.0	___	V

NOTES:	5632 tbl 09

1.VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 6 for details.

2.Applicable only for TMS, TDI and TRST inputs.

3.Outputs tested in tri-state mode.

DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(3) (VDD = 2.5V ± 100mV)

70T651/9S8(7)

70T651/9S10

70T651/9S12

70T651/9S15

Com'l Only

Com'l

Com'l

Com'l Only

& Ind(7)

& Ind

Symbol

Parameter

Test Condition

Version

Typ.(4)

Max.

Typ.(4)

Max.

Typ.(4)

Max.

Typ.(4)

Max.

Unit

IDD

Dynamic Operating

CEL and CER= VIL,

COM'L

S

350

475

300

405

300

355

225

305

mA

Current (Both

Outputs Disabled

IND

S

300

445

300

395

Ports Active)

f = fMAX(1)

____

____

____

____

ISB1(6)

Standby Current

CEL = CER = VIH

COM'L

S

115

140

90

120

75

105

60

85

mA

(Both Ports - TTL

f = fMAX(1)

IND

S

90

145

75

130

Level Inputs)

____

____

____

____

ISB2(6)

Standby Current

CE"A" = VIL and CE"B" = VIH(5)

COM'L

S

240

315

200

265

180

230

150

200

mA

(One Port - TTL

Active Port Outputs Disabled,

IND

S

200

290

180

255

Level Inputs)

f = fMAX(1)

____

____

____

____

ISB3

Full Standby Current

Both Ports CEL and

COM'L

S

2

10

2

10

2

10

2

10

mA

(Both Ports - CMOS

CER > VDD - 0.2V, VIN > VDD - 0.2V

IND

S

2

20

2

20

Level Inputs)

or VIN < 0.2V, f = 0(2)

____

____

____

____

ISB4(6)

Full Standby Current

CE"A" < 0.2V and CE"B" > VDD - 0.2V(5)

COM'L

S

240

315

200

265

180

230

150

200

mA

(One Port - CMOS

VIN > VDD - 0.2V or VIN < 0.2V, Active

IND

S

200

290

180

255

Level Inputs)

Port, Outputs Disabled, f = fMAX(1)

____

____

____

____

IZZ

Sleep Mode Current

ZZL = ZZR = VIH

COM'L

S

2

10

2

10

2

10

2

10

mA

(Both Ports - TTL

f = fMAX(1)

IND

S

2

20

2

20

Level Inputs)

____

____

____

____

NOTES:

5632 tbl 10

1.At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS" at input levels of GND to 3.3V.

2.f = 0 means no address or control lines change. Applies only to input at CMOS level standby.

3.Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 100mA (Typ).

5.CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL

CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQX - 0.2V

CEX > VDDQX - 0.2V means CE0X > VDDQX - 0.2V or CE1X < 0.2V. "X" represents "L" for left port or "R" for right port.

6.ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and /or ZZR = VIH.

7.8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

9