IDT IDT54FCT16652T, IDT54FCT16652AT, IDT54FCT16652CT, IDT54FCT16652ET, IDT54FCT162652T User Manual
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IDT54FCT162652ATEB
FAST CMOS 16-BIT BUS IDT54/74FCT16652T/AT/CT/ET |
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TRANSCEIVER/ |
IDT54/74FCT162652T/AT/CT/ET |
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REGISTERS |
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Integrated Device Technology, Inc.
FEATURES:
•Common features:
–0.5 MICRON CMOS Technology
–High-speed, low-power CMOS replacement for ABT functions
–Typical tSK(o) (Output Skew) < 250ps
–Low input and output leakage ≤1μA (max.)
–ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
–Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,15.7 mil pitch TVSOP and 25 mil pitch Cerpack
–Extended commercial range of -40°C to +85°C
–VCC = 5V ±10%
•Features for FCT16652T/AT/CT/ET:
–High drive outputs (-32mA IOH, 64mA IOL)
–Power off disable outputs permit “live insertion”
–Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C
•Features for FCT162652T/AT/CT/ET:
–Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
–Reduced system switching noise
–Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,TA = 25°C
DESCRIPTION:
The FCT16652T/AT/CT/ET and FCT162652T/AT/CT/ET 16-bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power de-
vices are organized as two independent 8-bit bus transceivers with 3-state D-type registers. For example, the xOEAB and xOEBA signals control the transceiver functions.
The xSAB and xSBA control pins are provided to select either real time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real time data. A LOW input level selects real-time data and a HIGH level selects stored data.
Data on the A or B data bus, or both, can be stored in the internal D-flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (xCLKAB or xCLKBA), regardless of the select or enable control pins. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin.
The FCT16652T/AT/CT/ET are ideally suited for driving high capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers.
The FCT162652T/AT/CT/ET have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times–reducing the need for external series terminating resistors. The FCT162652T/AT/CT/ET are plug-in replacements for the FCT16652T/AT/CT/ET and ABT16652 for on-board bus interface applications.
FUNCTIONAL BLOCK DIAGRAM
1OEAB |
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2OEAB |
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1OEBA |
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2OEBA |
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1CLKBA |
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2CLKBA |
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1SBA |
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2SBA |
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1CLKAB |
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2CLKAB |
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1SAB |
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2SAB |
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B REG |
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B REG |
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D |
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D |
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C |
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C |
1A1 |
A REG |
1B1 |
2A1 |
A REG |
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2B1 |
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D |
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D |
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C |
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C |
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TO 7 OTHER CHANNELS |
2549 drw 01 |
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TO 7 OTHER CHANNELS |
2549 drw 02 |
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The IDT logo is a registered trademark of Integrated Device Technology, Inc. |
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MILITARY AND COMMERCIAL TEMPERATURE RANGE |
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AUGUST 1996 |
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©1996 Integrated Device Technology, Inc. |
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DSC-2549/8 |
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1
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET |
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FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER |
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
PIN CONFIGURATIONS
1OEAB |
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1 |
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56 |
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1OEBA |
1CLKAB |
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2 |
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55 |
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1CLKBA |
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1SAB |
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3 |
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54 |
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1SBA |
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GND |
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4 |
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53 |
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GND |
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1A1 |
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5 |
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52 |
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1B1 |
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1A2 |
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6 |
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51 |
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1B2 |
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VCC |
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7 |
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50 |
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VCC |
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1A3 |
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8 |
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49 |
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1B3 |
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1A4 |
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9 |
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48 |
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1B4 |
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1A5 |
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10 |
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47 |
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1B5 |
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GND |
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11 |
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46 |
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GND |
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1A6 |
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12 |
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45 |
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1B6 |
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1A7 |
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13 |
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44 |
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1B7 |
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1A8 |
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14 |
SO56-1 |
43 |
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1B8 |
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2A1 |
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15 |
SO56-2 |
42 |
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2B1 |
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SO56-3 |
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2A2 |
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16 |
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41 |
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2B2 |
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2A3 |
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17 |
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40 |
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2B3 |
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GND |
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18 |
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39 |
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GND |
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2A4 |
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19 |
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38 |
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2B4 |
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2A5 |
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20 |
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37 |
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2B5 |
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2A6 |
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21 |
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36 |
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2B6 |
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VCC |
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22 |
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35 |
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VCC |
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2A7 |
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23 |
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34 |
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2B7 |
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2A8 |
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24 |
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33 |
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2B8 |
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GND |
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25 |
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32 |
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GND |
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2SAB |
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26 |
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31 |
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2SBA |
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2CLKAB |
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27 |
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30 |
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2CLKBA |
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2OEAB |
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28 |
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29 |
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2OEBA |
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SSOP/ |
2549 drw 03 |
TSSOP/TVSOP
TOP VIEW
1OEAB |
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1 |
56 |
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1OEBA |
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1CLKAB |
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2 |
55 |
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1CLKBA |
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1SAB |
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3 |
54 |
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1SBA |
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GND |
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4 |
53 |
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GND |
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1A1 |
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5 |
52 |
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1B1 |
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1A2 |
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6 |
51 |
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1B2 |
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VCC |
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7 |
50 |
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VCC |
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1A3 |
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8 |
49 |
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1B3 |
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1A4 |
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9 |
48 |
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1B4 |
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1A5 |
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10 |
47 |
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1B5 |
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GND |
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11 |
46 |
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GND |
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1A6 |
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12 |
45 |
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1B6 |
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1A7 |
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13 |
44 |
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1B7 |
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1A8 |
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14 |
E56-1 43 |
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1B8 |
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2A1 |
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15 |
42 |
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2B1 |
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2A2 |
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16 |
41 |
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2B2 |
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2A3 |
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17 |
40 |
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2B3 |
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GND |
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18 |
39 |
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GND |
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2A4 |
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19 |
38 |
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2B4 |
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2A5 |
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20 |
37 |
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2B5 |
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2A6 |
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21 |
36 |
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2B6 |
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VCC |
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22 |
35 |
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VCC |
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2A7 |
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23 |
34 |
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2B7 |
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2A8 |
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24 |
33 |
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2B8 |
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GND |
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25 |
32 |
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GND |
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2SAB |
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26 |
31 |
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2SBA |
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2CLKAB |
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27 |
30 |
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2CLKBA |
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2OEAB |
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28 |
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2OEBA |
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2549 drw 04 |
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CERPACK
TOP VIEW
2
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET |
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FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER |
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
PIN DESCRIPTION
Pin Names |
Description |
xAx |
Data Register A Inputs |
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Data Register B Outputs |
xBx |
Data Register B Inputs |
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Data Register A Outputs |
xCLKAB, xCLKBA |
Clock Pulse Inputs |
xSAB, xSBA |
Output Data Source Select Inputs |
xOEAB, xOEBA |
Output Enable Inputs |
2549 tbl 01
FUNCTION TABLE(2)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol |
Parameter(1) |
Conditions |
Typ. |
Max. |
Unit |
CIN |
Input |
VIN = 0V |
4.5 |
6.0 |
pF |
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Capacitance |
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CI/O |
I/O |
VOUT = 0V |
5.5 |
8.0 |
pF |
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Capacitance |
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NOTE: |
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2549 lnk 02 |
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1. This parameter is measured at characterization but not tested.
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Inputs |
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Data I/O(1) |
Operation or Function |
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xOEAB |
xOEBA |
xCLKAB |
xCLKBA |
xSAB |
xSBA |
xAx |
xBx |
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L |
H |
H or L |
H or L |
X |
X |
Input |
Input |
Isolation |
L |
H |
− |
− |
X |
X |
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Store A and B Data |
X |
H |
− |
H or L |
X |
X |
Input |
Unspecified(1) |
Store A, Hold B |
H |
H |
− |
− |
X(2) |
X |
Input |
Output |
Store A in Both Registers |
L |
X |
H or L |
− |
X |
X |
Unspecified(1) |
Input |
Hold A, Store B |
L |
L |
− |
− |
X |
X(2) |
Output |
Input |
Store B in both Registers |
L |
L |
X |
X |
X |
L |
Output |
Input |
Real Time B Data to A Bus |
L |
L |
X |
H or L |
X |
H |
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Stored B Data to A Bus |
H |
H |
X |
X |
L |
X |
Input |
Output |
Real Time A Data to B Bus |
H |
H |
H or L |
X |
H |
X |
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Stored A Data to B Bus |
H |
L |
H or L |
H or L |
H |
H |
Output |
Output |
Stored A Data to B Bus and |
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Stored B Data to A Bus |
NOTES:
1. |
The data output functions may be enabled or disabled by various signals at the xOEAB or xOEBA inputs. |
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Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH |
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transition on the clocks inputs. |
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2. |
Select control = L: clocks can occur simultaneously. |
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Select control = H: clocks must be staggered to load both registers. |
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3. |
H = HIGH Voltage Level |
ABSOLUTE MAXIMUM RATINGS(1) |
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L = LOW Voltage Level |
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X = Don't care |
Symbol |
Description |
Max. |
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− = LOW-to-HIGH Transition |
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VTERM(2)
Terminal Voltage with Respect to 
–0.5 to +7.0
GND
VTERM(3) Terminal Voltage with Respect to
GND
2549 tbl 03
Unit
V
V
TSTG |
Storage Temperature |
–65 to +150 |
°C |
IOUT |
DC Output Current |
–60 to +120 |
mA |
NOTES: |
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2549 lnk 04 |
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.All device terminals except FCT162XXXT Output and I/O terminals.
3.Output and I/O terminals for FCT162XXXT.
3
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