Integrated Device Technology Inc IDT7006L15F, IDT7006L15G, IDT7006L20J, IDT7006L20JB, IDT7006L20PF Datasheet

I/O

Control

Address

Decoder

MEMORY

ARRAY

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

Address

Decoder

I/O

Control

R/

W

L

CE

L

OE

L

BUSY

L

A

13L

A

0L

2739 drw 01

I/O

0L

- I/O

7L

CE

L

OE

L

R/

W

L

SEM

L

INT

L

M/

S

BUSY

R

I/O

0R

-I/O

7R

A

13R

A

0R

SEM

R

INT

R

CE

R

OE

R

(2)

(1,2)

(2)

R/

W

R

CE

R

OE

R

R/

W

R

14

Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996

IDT7006S/L

HIGH-SPEED

16K x 8 DUAL-PORT

STATIC RAM

FEATURES:

• True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

• High-speed access

— Military: 20/25/35/55/70ns (max.)

— Commercial: 15/17/20/25/35/55ns (max.)

• Low-power operation

— IDT7006S

Active: 750mW (typ.)

Standby: 5mW (typ.)

— IDT7006L

Active: 750mW (typ.)

Standby: 1mW (typ.)

• IDT7006 easily expands data bus width to 16 bits or

more using the Master/Slave select when cascading

more than one device

•M/

S

= H for

BUSY

output flag on Master,

M/

S

= L for

BUSY

input on Slave

• Busy and Interrupt Flags

• On-chip port arbitration logic

• Full on-chip hardware support of semaphore signaling

between ports

• Fully asynchronous operation from either port

• Devices are capable of withstanding greater than 2001V

electrostatic discharge

• Battery backup operation—2V data retention

• TTL-compatible, single 5V (±10%) power supply

• Available in a 68-pin PGA, a 68-pin quad flatpack, a 68-

pin PLCC, and a 64-pin TQFP

• Industrial temperature range (–40°C to +85°C) is avail-

able, tested to military electrical specifications

DESCRIPTION:

The IDT7006 is a high-speed 16K x 8 Dual-Port Static

RAM. The IDT7006 is designed to be used as a stand-alone

Dual-Port RAM or as a combination MASTER/SLAVE Dual-

Port RAM for 16-bit-or-more word systems. Using the IDT

MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider

FUNCTIONAL BLOCK DIAGRAM

1

NOTES:

1. (MASTER):

BUSY

is

output;

(SLAVE):

BUSY

is input.

2.

BUSY

outputs

and

INT

outputs are

non-tri-stated

push-pull.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.07

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.07 2

IDT7006S/L

HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

memory system applications results in full-speed, error-free

operation without the need for additional discrete logic.

This device provides two independent ports with separate

control, address, and I/O pins that permit independent,

asynchronous access for reads or writes to any location in

memory. An automatic power down feature controlled by

CE

permits the on-chip circuitry of each port to enter a very low

standby power mode.

Fabricated using IDT’s CMOS high-performance technol-

ogy, these devices typically operate on only 750mW of power.

Low-power (L) versions offer battery backup data retention

capability with typical power consumption of 500µW from a 2V

battery.

The IDT7006 is packaged in a ceramic 68-pin PGA, a 68-

pin quad flatpack, a 68-pin PLCC, and a 64-pin TQFP (thin

plastic quad flatpack) . Military grade product is manufactured

in compliance with the latest revision of MIL-STD-883, Class

B, making it ideally suited to military temperature applications

demanding the highest level of performance and reliability.

PIN CONFIGURATIONS

(1,2)

INDEX

IDT7006

PN-64

TQFP

TOP VIEW

(3)

8

9

10

11

12

13

14

15

16

1

2

3

4

5

6

7

46

45

44

43

42

41

40

39

38

37

36

35

34

47

48

33

17

18

19

20

32

31

30

29

28

27

26

25

24

23

22

21

49

50

51

52

63

62

61

60

59

58

57

56

55

54

53

64

I/O

2L

V

CC

GND

A

4R

BUSY

L

BUSY

R

INT

R

INT

L

GND

M/

S

OE

L

A

5L

I/O

1L

R/

W

L

CE

L

SEM

L

V

CC

OE

R

CE

R

R/

W

R

SEM

R

A

12R

GND

I/O

3L

I/O

4L

I/O

5L

I/O

6L

I/O

7L

I/O

0R

I/O

1R

I/O

2R

V

CC

I/O

3R

I/O

4R

I/O

5R

I/O

6R

I/O

7R

A

11R

A

10R

A

9R

A

8R

A

7R

A

6R

A

5R

A

3R

A

2R

A

1R

A

0R

A

0L

A

1L

A

2L

A

3L

A

4L

A

6L

A

7L

A

8L

A

9L

A

10L

A

11L

A

12L

I/O

0L

2739 drw 03

A

13R

A

13L

2739 drw 02

12

13

14

15

16

17

18

INDEX

19

20

21

22

98765432168676665

27 28 29 30 31 32 33 34 35 36 37 38 39

V

CC

V

CC

I/O

1R

I/O

2R

I/O

3R

I/O

4R

INT

L

GND

A

4L

A

3L

A

2L

A

1L

A

0L

A

3R

A

0R

A

1R

A

2R

I/O

2L

A

5L

R/

W

L

11

10

M/

S

23

24

25

26

40 41 42 43

58

57

56

55

54

53

52

51

50

49

48

59

60

47

46

45

44

64 63 62 61

I/O

3L

GND

I/O

0R

V

CC

A

4R

BUSY

L

GND

BUSY

R

INT

R

A

12R

I/O

7R

N/C

GND

OE

R

R/

W

R

SEM

R

CE

R

OE

L

SEM

L

CE

L

N/C

I/O

0L

I/O

1L

IDT7006

J68-1

F68-1

PLCC / FLATPACK

TOP VIEW

(3)

I/O

4L

I/O

5L

I/O

6L

I/O

7L

I/O

5R

I/O

6R

N/C

A

12L

N/C

A

11R

A

10R

A

9R

A

8R

A

7R

A

6R

A

5R

A

11L

A

10L

A

9L

A

8L

A

7L

A

6L

A

13R

A

13L

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the the actual part-marking.

IDT7006S/L

HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.07 3

Left Port Right Port Names

CE

L

CE

R Chip Enable

R/

W

L R/

W

R Read/Write Enable

OE

L

OE

R Output Enable

A

0L – A13L A0R – A13R Address

I/O

0L – I/O7L I/O0R – I/O7R Data Input/Output

SEM

L

SEM

R Semaphore Enable

INT

L

INT

R Interrupt Flag

BUSY

L

BUSY

R Busy Flag

M/

S

Master or Slave Select

V

CC Power

GND Ground

PIN NAMES

NOTES:

1. All V

CC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. This text does not indicate orientation of the actual part-marking.

2739 tbl 01

2739 drw 04

51 50 48 46 44 42 40 38 36

53

55

57

59

61

63

65

67

68

66

13579

11 13 15

20

22

24

26

28

30

32

35

IDT7006

G68-1

68-PIN PGA

TOP VIEW

(3)

ABCDEFGH JKL

47 45 43 41 34

21

23

25

27

29

31

33

246810121416

18 19

17

56

58

60

62

64

11

10

09

08

07

06

05

04

03

02

01

52

54

49 39 37

A

5L

INT

L

N/C

SEM

L

CE

L

V

CC

OE

L

R/

W

L

I/O

0L

N/C

GND GND

I/O

0R

V

CC

N/C

OE

R

R/

W

R

SEM

R

CE

R

GND

BUSY

R

BUSY

L

M/

S

INT

R

N/C

GND

A

1R

INDEX

A

4L

A

2L

A

0L

A

3R

A

2R

A

4R

A

5R

A

7R

A

6R

A

9R

A

8R

A

11R

A

10R

A

12R

A

0R

A

7L

A

6L

A

3L

A

1L

A

9L

A

8L

A

11L

A

10L

A

12L

V

CC

I/O

2R

I/O

3R

I/O

5R

I/O

6R

I/O

1R

I/O

4R

I/O

7R

I/O

1L

I/O

2L

I/O

4L

I/O

7L

I/O

3L

I/O

5L

I/O

6L

A

13R

A

13L

PIN CONFIGURATIONS (CONT'D)

(1,2)

6.07 4

IDT7006S/L

HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

(1)

(TA = +25°C, f = 1.0MHz)TQFP PACKAGE

Symbol Parameter Conditions

(2)

Max. Unit

C

IN Input Capacitance VIN = 3dV 9 pF

C

OUT Output VOUT = 3dV 10 pF

Capacitance

NOTES: 2739 tbl 07

1. This parameter is determined by device characterization, but is not

production tested.

2. 3dv references the interpolated capacitance when the input and output

signals switch from 0V to 3V or from 3V to 0V.

TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL

Inputs

(1)

Outputs

CECE

CE

R/

WW

W

OEOE

OE

SEMSEM

SEM

I/O

0-7 Mode

H X X H High-Z Deselected: Power-Down

L L X H DATA

IN Write to Memory

L H L H DATA

OUT Read Memory

X X H X High-Z Outputs Disabled

NOTE: 2739 tbl 02

1. A0L — A13L is not equal to A0R — A13R.

TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL

(1)

Inputs Outputs

CECE

CE

R/

WW

W

OEOE

OE

SEMSEM

SEM

I/O

0-7 Mode

H H L L DATA

OUT Read Data in Semaphore Flag Data Out

H

u

X L DATA

IN Write I/O0 into Semaphore Flag

L X X L — Not Allowed

2739 tbl 03

RECOMMENDED DC OPERATING

CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V

V

IH Input High Voltage 2.2 — 6.0

(2)

V

IL Input Low Voltage –0.5

(1)

— 0.8 V

NOTES: 2739 tbl 06

1. VIL≥ -1.5V for pulse width less than 10ns.

2. V

TERM must not exceed Vcc + 0.5V.

RECOMMENDED OPERATING

TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND V

CC

Military –55°C to +125°C 0V 5.0V ± 10%

Commercial 0°C to +70°C 0V 5.0V ± 10%

2739 tbl 05

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

V

TERM

(2)

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V

with Respect

to GND

T

A Operating 0 to +70 –55 to +125 °C

Temperature

T

BIAS Temperature –55 to +125 –65 to +135 °C

Under Bias

T

STG Storage –55 to +125 –65 to +150 °C

Temperature

I

OUT DC Output 50 50 mA

Current

NOTES: 2739 tbl 04

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect reliability.

2. V

TERM must not exceed Vcc + 0.5V for more than 25% of the cycle time

or 10ns maximum, and is limited to

< 20mA for the period of VTERM < Vcc

+ 0.5V.

NOTE:

1. There are eight semaphore flags written to via I/O

0 and read from I/O0 - I/O15. These eight semaphores are addressed by A0 - A2.

IDT7006S/L

HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.07 5

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(VCC = 5.0V ± 10%)

IDT7006S IDT7006L

Symbol Parameter Test Conditions Min. Max. Min. Max. Unit

|I

LI| Input Leakage Current

(1)

VCC = 5.5V, VIN = 0V to VCC —10—5µA

|I

LO| Output Leakage Current

CE

= VIH, VOUT = 0V to VCC —10—5µA

V

OL Output Low Voltage IOL = 4mA — 0.4 — 0.4 V

V

OH Output High Voltage IOH = -4mA 2.4 — 2.4 — V

2739 tbl 08

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(1)

(VCC = 5.0V ± 10%)

7006X15 7006X17 7006X20 7006X25

Test

Com'l. Only Com'l. Only

Symbol Parameter Condition Version

Typ.

(2)

Max.

Typ.

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max.

Unit

I

CC Dynamic Operating

CE

= VIL, Outputs Open MIL. S — — — — 160 370 155 340 mA

Current

SEM

= V

IH L — — — — 150 320 145 280

(Both Ports Active) f = f

MAX

(3)

COM.

S 170 310 170 310 160 290 155 265

L 160 260 160 260 150 240 145 220

I

SB1 Standby Current

CE

L =

CE

R = VIH MIL. S — — — — 20 90 16 80 mA

(Both Ports — TTL

SEM

R =

SEM

L = VIH L — — — — 10 70 10 65

Level Inputs f = f

MAX

(3)

COM.

S 20 60 20 60 20 60 16 60

L 10 50 10 50 10 50 10 50

I

SB2 Standby Current

CE

"A"=VIL and

CE

"B"=VIH

(5)

MIL. S — — — — 95 240 90 215 mA

(One Port — TTL Active Port Outputs Open

L — — — — 85 210 80 180

Level Inputs) f = f

MAX

(3)

COM.

S 105 190 105 190 95 180 90 170

SEM

R =

SEM

L > VIH L 95 160 95 160 85 150 80 140

I

SB3 Full Standby Current Both Ports

CE

L and MIL. S — — — — 1.0 30 1.0 30 mA

(Both Ports — All

CE

R > VCC - 0.2V L — — — — 0.2 10 0.2 10

CMOS Level Inputs) V

IN > VCC - 0.2V or

COM.

S 1.0 15 1.0 15 1.0 15 1.0 15

V

IN < 0.2V, f = 0

(4)

L 0.2 5 0.2 5 0.2 5 0.2 5

SEM

R =

SEM

L > VCC-0.2V

I

SB4 Full Standby Current

CE

"A" < 0.2V and MIL. S — — — — 90 225 85 200 mA

(One Port — All

CE

"B" > VCC - 0.2V

(5)

CMOS Level Inputs)

SEM

R =

SEM

L > VCC-0.2V L — — — — 80 200 75 170

V

IN > VCC - 0.2V or

COM

.S100 170 100 170 90 155 85 145

V

IN < 0.2v

Active Port Outputs Open,

L 90 140 90 140 80 130 75 120

f = f

MAX

(3)

NOTE:

1. At Vcc

≤ 2.0V input leakages are undefined.

NOTES: 2739 tbl 09

1. "X" in part numbers indicates power rating (S or L).

2. V

CC = 5V, TA = +25°C, and are not production tested. ICC DC = 120mA (typ.).

3. At f = f

MAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A"may be either left or right port. Port "B" is the port opposite port "A".

6.07 6

IDT7006S/L

HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(1)

(Cont'd.) (VCC = 5.0V ± 10%)

7006X35 7006X55 7006X70

Test Mil Only

Symbol Parameter Condition Version Typ.

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Unit

I

CC Dynamic Operating

CE

= VIL, Outputs Open MIL. S 150 300 150 300 140 300 mA

Current

SEM

= V

IH L 140 250 140 250 130 250

(Both Ports Active) f = f

MAX

(3)

COM’L. S 150 250 150 250 — —

L 140 210 140 210 — —

I

SB1 Standby Current

CE

L =

CE

R = VIH MIL. S 13 80 13 80 10 80 mA

(Both Ports — TTL

SEM

R =

SEM

L = VIH L10 65 10 65 8 65

Level Inputs) f = f

MAX

(3)

COM’L. S 13 60 13 60 — —

L10 50 10 50 — —

I

SB2 Standby Current

CE

"A"=VIL and

CE

L"B"=VIH

(5)

MIL. S 85 190 85 190 80 190 mA

(One Port — TTL Active Port Outputs Open, L 75 160 75 160 70 160

Level Inputs) f = f

MAX

(3)

COM’L. S 85 155 85 155 — —

SEM

R =

SEM

L = VIH L 75 130 75 130 — —

I

SB3 Full Standby Current Both Ports

CE

L and MIL. S 1.0 30 1.0 30 1.0 30 mA

(Both Ports — All

CE

R > VCC - 0.2V L 0.2 10 0.2 10 0.2 10

CMOS Level Inputs) V

IN > VCC - 0.2V or COM’L. S 1.0 15 1.0 15 — —

V

IN < 0.2V, f = 0

(4)

L 0.2 5 0.2 5 — —

SEM

R =

SEM

L≥ VCC-0.2V

I

SB4 Full Standby Current

CE

"A" < 0.2V and MIL. S 80 175 80 175 75 175 mA

(One Port — All

CE

"B" > VCC - 0.2V

(5)

CMOS Level Inputs)

SEM

R =

SEM

L≥ VCC - 0.2V L 70 150 70 150 65 150

V

IN > VCC - 0.2V or COM’L. S 80 135 80 135 — —

V

IN < 0.2V

Active Port Outputs Open, L 70 110 70 110 — —

f = f

MAX

(3)

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)

(VLC = 0.2V, VHC = VCC - 0.2V)

(4)

Symbol Parameter Test Condition Min. Typ.

(1)

Max. Unit

V

DR VCC for Data Retention VCC = 2V 2.0 — — V

I

CCDR Data Retention Current

CE

≥ VHC MIL. — 100 4000 µA

V

IN ≥ VHC or ≤ VLC COM’L. — 100 1500

t

CDR

(3)

Chip Deselect to Data Retention Time

SEM

≥ VHC 0——ns

t

R

(3)

Operation Recovery Time tRC

(2)

——ns

NOTES: 2739 tbl 11

1. TA = +25°C, VCC = 2V, and are not production tested.

2. t

RC = Read Cycle Time

3. This parameter is guaranteed by characterization, but are not production tested.

4. At Vcc = 2V input leakages are undefined

DATA RETENTION MODE

V

CC

CE

2739 drw 05

4.5V

t

CDR

t

R

V

IH

V

DR

V

IH

4.5V

V

DR

2V

≥

DATA RETENTION WAVEFORM

NOTES: 2739 tbl 10

1. "X" in part numbers indicates power rating (S or L).

2. V

CC = 5V, TA = +25°C, and are not production tested. ICC DC =120mA (typ).

3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B"is the opposite from port "A".