Integrated Device Technology Inc IDT71256L120DB, IDT71256L120LB, IDT71256L120PB, IDT71256L120TDB, IDT71256L120YB Datasheet
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CMOS STATIC RAM |
IDT71256S |
256K (32K x 8-BIT) |
IDT71256L |
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Integrated Device Technology, Inc.
FEATURES:
•High-speed address/chip select time
—Military: 25/30/35/45/55/70/85/100/120/150ns (max.)
—Commercial: 20/25/35/45ns (max.) Low Power only.
•Low-power operation
•Battery Backup operation — 2V data retention
•Produced with advanced high-performance CMOS technology
•Input and output directly TTL-compatible
•Available in standard 28-pin (300 or 600 mil) ceramic DIP, 28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ and 32-pin LCC
•Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT71256 is a 262,144-bit high-speed static RAM organized as 32K x 8. It is fabricated using IDT’s highperformance, high-reliability CMOS technology.
Address access times as fast as 20ns are available with power consumption of only 350mW (typ.). The circuit also offers a reduced power standby mode. When CS goes HIGH, the circuit will automatically go to, and remain in, a low-power standby mode as long as CSremains HIGH. In the full standby mode, the low-power device consumes less than 15μW, typically. This capability provides significant system level power and cooling savings. The low-power (L) version also offers a battery backup data retention capability where the circuit typically consumes only 5μW when operating off a 2V battery.
The lDT71256 is packaged in a 28-pin (300 or 600 mil) ceramic DIP, a 28-pin 300 mil J-bend SOlC, and a 28-pin (600 mil) plastic DIP, and 32-pin LCC providing high board-level packing densities.
The IDT71256 military RAM is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0
ADDRESS
DECODER
A14
I/O 0
INPUT DATA
CIRCUIT
I/O 7
CS 
OE CONTROL
CIRCUIT
WE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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V CC |
262,144 BIT |
GND |
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MEMORY ARRAY |
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I/O CONTROL
2946 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
AUGUST 1996 |
©1996 Integrated Device Technology, Inc. |
DSC-2946/7 |
7.2 |
1 |
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IDT71256 S/L |
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CMOS STATIC RAM 256K (32K x 8-BIT) |
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
PIN CONFIGURATIONS
A14 |
1 |
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28 |
V CC |
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A12 |
2 |
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27 |
WE |
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A7 |
3 |
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26 |
A13 |
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A6 |
4 |
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25 |
A8 |
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A5 |
5 |
D28-3 |
24 |
A9 |
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A4 |
6 |
23 |
A11 |
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A3 |
7 |
P28-1 |
22 |
OE |
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P28-2 |
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A2 |
8 |
21 |
A10 |
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D28-1 |
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A1 |
9 |
20 |
CS |
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SO28-5 |
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A0 |
10 |
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19 |
I/O 7 |
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I/O 0 |
11 |
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18 |
I/O 6 |
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I/O 1 |
12 |
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17 |
I/O 5 |
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I/O 2 |
13 |
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16 |
I/O 4 |
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GND |
14 |
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15 |
I/O 3 |
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2946 drw 02 |
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DIP/SOJ
TOP VIEW
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A7 |
A12 |
14A |
NC VCC WE |
A |
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INDEX |
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13 |
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32 31 30 |
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A6 |
5 |
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A8 |
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A5 |
6 |
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28 |
A9 |
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A4 |
7 |
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27 |
A11 |
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A3 |
8 |
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L32-1 |
26 |
NC |
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A2 |
9 |
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25 |
OE |
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A1 |
10 |
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24 |
A10 |
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A0 |
11 |
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23 |
CS |
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NC |
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12 |
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22 |
I/O7 |
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I/O0 |
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13 |
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21 |
I/O6 |
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14 15 16 |
17 18 19 20 |
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I/O1 |
I/O2 |
GND |
NC I/O3 I/O4 |
I/O5 |
2946 drw 03 |
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32-Pin LCC
TOP VIEW
PIN DESCRIPTIONS
Name |
Description |
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A0–A14 |
Addresses |
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I/O0–I/O7 |
Data Input/Output |
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CS |
Chip Select |
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WE |
Write Enable |
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OE |
Output Enable |
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GND |
Ground |
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VCC |
Power |
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2946 tbl 01
TRUTH TABLE(1)
WE |
CS |
OE |
I/O |
Function |
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X |
H |
X |
High-Z |
Standby (ISB) |
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X |
VHC |
X |
High-Z |
Standby (ISB1) |
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H |
L |
H |
High-Z |
Output Disabled |
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H |
L |
L |
DOUT |
Read Data |
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L |
L |
X |
DIN |
Write Data |
NOTE: |
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2946 tbl 02 |
1. H = VIH, L = VIL, X = Don’t Care
ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Rating |
Com’l. |
Mil. |
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Unit |
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VTERM |
Terminal Voltage |
–0.5 to +7.0 |
–0.5 to +7.0 |
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V |
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with Respect |
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to GND |
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TA |
Operating |
0 to +70 |
–55 to +125 |
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°C |
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Temperature |
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TBIAS |
Temperature |
–55 to +125 |
–65 to +135 |
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°C |
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Under Bias |
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TSTG |
Storage |
–55 to +125 |
–65 to +150 |
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°C |
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Temperature |
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PT |
Power Dissipation |
1.0 |
1.0 |
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W |
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IOUT |
DC Output |
50 |
50 |
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mA |
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Current |
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NOTE: |
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2946 tbl 03 |
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1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol |
Parameter(1) |
Conditions |
Max. |
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Unit |
CIN |
Input Capacitance |
VIN = 0V |
11 |
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pF |
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CI/O |
I/O Capacitance |
VOUT = 0V |
11 |
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pF |
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NOTE: |
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2946 tbl 04 |
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1.This parameter is determined by device characterization, but is not production tested.
7.2 |
2 |
IDT71256S/L |
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CMOS STATIC RAM 256K (32K x 8-BIT) |
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade |
Temperature |
GND |
VCC |
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Military |
–55°C to +125°C |
0V |
5.0V ± 10% |
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Commercial |
0°C to +70°C |
0V |
5.0V ± 10% |
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2946 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
Symbol |
Parameter |
Min. |
Typ. |
Max. |
Unit |
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VCC |
Supply Voltage |
4.5 |
5.0 |
5.5 |
V |
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GND |
Supply Voltage |
0 |
0 |
0 |
V |
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VIH |
Input High Voltage |
2.2 |
— |
6.0 |
V |
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VIL |
Input Low Voltage |
–0.5(1) |
— |
0.8 |
V |
NOTE: |
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2946 tbl 06 |
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1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS(1, 2)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
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71256S/L20 |
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71256S/L25 |
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71256S/L30 |
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71256S/L35 |
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Symbol |
Parameter |
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Power |
Com’l. |
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Mil. |
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Com’l. |
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Mil. |
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Com’l. |
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Mil. |
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Com’l. |
Mil. |
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Unit |
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ICC |
Dynamic Operating Current |
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S |
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— |
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— |
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— |
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150 |
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— |
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145 |
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— |
140 |
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mA |
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CS £ VIL, Outputs Open |
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VCC = Max., f = fMAX(2) |
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L |
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135 |
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— |
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115 |
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130 |
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— |
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125 |
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105 |
120 |
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ISB |
Standby Power Supply |
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S |
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— |
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— |
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— |
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20 |
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— |
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20 |
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— |
20 |
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mA |
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Current (TTL Level) |
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CS ³ VIH, VCC = Max., |
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L |
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3 |
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— |
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3 |
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3 |
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— |
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3 |
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3 |
3 |
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Outputs Open, f = fMAX(2) |
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ISB1 |
Full Standby Power Supply |
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S |
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— |
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— |
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— |
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20 |
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— |
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20 |
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— |
20 |
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mA |
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Current (CMOS Level) |
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CS ³ VHC, VCC = Max., f = 0 |
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L |
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0.4 |
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— |
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0.4 |
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1.5 |
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— |
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1.5 |
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0.4 |
1.5 |
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71256S/L45 |
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71256S/L55 |
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71256S/L70 |
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71256S/L85(3) |
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71256S/L100(3) |
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Symbol |
Parameter |
Power |
Com’l. |
Mil. |
Com’l. |
Mil. |
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Com’l. |
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Mil. |
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Com’l. |
Mil. |
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Com'l. |
Mil. |
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Unit |
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ICC |
Dynamic Operating Current |
S |
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— |
135 |
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— |
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135 |
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— |
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135 |
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— |
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135 |
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— |
135 |
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mA |
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CS £ VIL, Outputs Open |
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VCC = Max., f = fMAX(2) |
L |
100 |
115 |
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— |
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115 |
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— |
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115 |
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— |
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115 |
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— |
115 |
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ISB |
Standby Power Supply |
S |
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— |
20 |
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— |
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20 |
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— |
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20 |
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— |
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20 |
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— |
20 |
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mA |
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Current (TTL Level) |
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CS ³ VIH, VCC = Max., |
L |
3 |
3 |
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— |
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3 |
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— |
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3 |
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— |
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3 |
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— |
3 |
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Outputs Open, f = fMAX(2) |
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ISB1 |
Full Standby Power Supply |
S |
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— |
20 |
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— |
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20 |
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— |
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20 |
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— |
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20 |
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— |
20 |
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mA |
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Current (CMOS Level) |
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CS ³ VHC, VCC = Max., f = 0 |
L |
0.4 |
1.5 |
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— |
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1.5 |
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— |
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1.5 |
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— |
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1.5 |
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— |
1.5 |
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NOTES: |
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2946 tbl 07 |
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1.All values are maximum guaranteed values.
2.fMAX = 1/tRC, all address inputs cycling at fMAX; f = 0 means no address pins are cycling.
3.Also available: 120 and 150 ns military devices.
7.2 |
3 |
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