Integrated Device Technology Inc IDT70T633S012BFI, IDT70T633S012DD, IDT70T633S012DDI, IDT70T633S015BC, IDT70T633S015BF Datasheet

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				HIGH-SPEED 2.5V	PRELIMINARY
				512/256K x 18


				ASYNCHRONOUS DUAL-PORT	IDT70T633/1S

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

Features							Full hardware support of semaphore signaling between
	True Dual-Port memory cells which allow simultaneous						ports on-chip
	access of the same memory location						ports on-chip
	access of the same memory location						On-chip port arbitration logic
	High-speed access						Fully asynchronous operation from either port
	–	Commercial: 8/10/12/15ns (max.)					Separate byte controls for multiplexed bus and bus
	–	Industrial: 10/12ns (max.)					matching compatibility
	RapidWrite Mode simplifies high-speed consecutive write						Sleep Mode Inputs on both ports
	cycles						Supports JTAG features compliant to IEEE 1149.1 in
	Dual chip enables allow for depth expansion without						BGA-208 and BGA-256 packages
	external logic						BGA-208 and BGA-256 packages
	external logic						Single 2.5V (±100mV) power supply for core
	IDT70T633/1 easily expands data bus width to 36 bits or						LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
	more using the Master/Slave select when cascading more						power supply for I/Os and control signals on each port
	than one device						power supply for I/Os and control signals on each port
	than one device						Available in a 256-ball Ball Grid Array, 144-pin Thin Quad
	M/S = VIH for BUSY output flag on Master,						Flatpack and 208-ball fine pitch Ball Grid Array
	M/S = VIL for BUSY input on Slave						Flatpack and 208-ball fine pitch Ball Grid Array
	M/S = VIL for BUSY input on Slave						Industrial temperature range (–40°C to +85°C) is available
	Busy and Interrupt Flags						for selected speeds
Functional Block Diagram							for selected speeds
Functional Block Diagram
		UBL							UBR
		LBL							LBR
		R/WL							R/WR
				B B		B	B
				E E		E	E
		CE0L		0	1	1	0		CE0R
		CE0L		L L		R R			CE0R
		CE1L							CE1R
		OEL							OER
				Dout0-8_L		Dout0-8_R
				Dout9-17_L Dout9-17_R
				512/256K x 18
					MEMORY
					ARRAY
		I/O0L- I/O17L		Din_L			Din_R		I/O0R - I/O17R
									I/O0R - I/O17R
		(1)	Address					Address	A18R(1)
		A18L	Address	ADDR_L		ADDR_R		Address
			Decoder	ADDR_L		ADDR_R		Decoder	A0R
		A0L	Decoder					Decoder	A0R

OEL	ARBITRATION	OER
CE0L	INTERRUPT	CE0R
CE0L	SEMAPHORE	CE1R
CE1L	SEMAPHORE
CE1L	LOGIC
R/WL	LOGIC	R/WR
R/WL		R/WR
BUSYL(2,3)
SEML	M/S
SEML
INTL(3)

TDI	JTAG	TCK

TDO		TMS

		TRST

BUSYR(2,3)

SEMR

INTR(3)

NOTES:		ZZL(4)	ZZ	ZZR(4)
			CONTROL
			LOGIC
1.	Address A18x is a NC for IDT70T631.			5670 drw 01
1.	Address A18x is a NC for IDT70T631.			5670 drw 01
2.	BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
3	BUSY and INT are non-tri-state totem-pole outputs (push-pull).
4.	The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the
	sleep mode pins themselves (ZZx) are not affected during sleep mode.			NOVEMBER 2003

DSC-5670/3

IDT70T633/1S	Preliminary
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

Description

The IDT70T633/1 is a high-speed 512/256K x 18 Asynchronous Dual-Port Static RAM. The IDT70T633/1 is designed to be used as a stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic.

This device provides two independent ports with separate control, address,andI/Opinsthatpermitindependent,asynchronousaccessfor reads or writes to any location in memory. An automatic power down

feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.

TheIDT70T651/9hasaRapidWriteModewhichallowsthedesigner to perform back-to-back write operations without pulsing the R/W input each cycle. This is especially significant at the 8 and 10ns cycle times of the IDT70T651/9, easing design considerations at these high performancelevels.

The70T633/1cansupportanoperatingvoltageofeither3.3Vor2.5V on one or both ports, controlled by the OPT pins. The power supply for the core of the device (VDD) remains at 2.5V.

Integrated Device Technology Inc IDT70T633S012BFI, IDT70T633S012DD, IDT70T633S012DDI, IDT70T633S015BC, IDT70T633S015BF Datasheet

IDT70T633/1S

Preliminary

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Configuration(1,2,3)

70T633/1BC

BC-256(5,6)

256-Pin BGA

03/13/03

Top View

A10

A11

A12

A13

A14

A15

A16

TDI

A17L

A14L

A11L

A8L

CE1L

OEL

INTL

A5L

A2L

A0L

B10

B11

B12

B13

B14

B15

B16

TDO

A18L(4)

A15L

A12L

A9L

UBL

CE0L

R/WL

A4L

A1L

C10

C11

C12

C13

C14

C15

C16

I/O9L

VSS

A16L

A13L

A10L

A7L

LBL

SEML

BUSYL

A6L

A3L

OPTL

I/O8L

D10

D11

D12

D13

D14

D15

D16

I/O9R

VDD

VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR

VDD

I/O8R

E10

E11

E12

E13

E14

E15

E16

I/O10R I/O10L

VDDQL

VDD

VSS

VDD

VDDQR

I/O7L

I/O7R

F10

F11

F12

F13

F14

F15

F16

I/O11L

I/O11R VDDQL

VDD

VSS

VDD

VDDQR

I/O6R

I/O6L

G10

G11

G12

G13

G14

G15

G16

I/O12L VDDQR

VSS

VDDQL

I/O5L

H10

H11

H12

H13

H14

H15

H16

I/O12R

VDDQR

VSS

VDDQL

I/O5R

J10

J11

J12

J13

J14

J15

J16

I/O13L I/O14R I/O13R VDDQL

ZZR

VSS

ZZL

VDDQR

I/O4R

I/O3R

I/O4L

K10

K11

K12

K13

K14

K15

K16

I/O14L VDDQL

VSS

VDDQR

I/O3L

L10

L11

L12

L13

L14

L15

L16

I/O15L

I/O15R VDDQR

VDD

VSS

VDD

VDDQL

I/O2L

I/O2R

M10

M11

M12

M13

M14

M15

M16

I/O16R I/O16L

VDDQR

VDD

VSS

VDD

VDDQL

I/O1R

I/O1L

N10

N11

N12

N13

N14

N15

N16

I/O17R

VDD

VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL

VDD

I/O0R

P10

P11

P12

P13

P14

P15

P16

I/O17L

TMS

A16R

A13R

A10R

A7R

LBR

SEMR BUSYR

A6R

A3R

I/O0L

R10

R11

R12

R13

R14

R15

R16

TRST A18R(4)

A15R

A12R

A9R

UBR

CE0R

R/WR M/S

A4R

A1R

OPTR

T10

T11

T12

T13

T14

T15

T16

NC TCK NC A17R

A14R

A11R

A8R

CE1R

OER

INTR

A5R

A2R

A0R

NOTES:

5670 drw 02c

1.	All VDD pins must be connected to 2.5V power supply.	,
2.	All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is	,
2.
	set to VSS (0V).
3.	All VSS pins must be connected to ground supply.
4.	A18X is a NC for IDT70T631.
5.	Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6.	This package code is used to reference the package diagram.

IDT70T633/1S	Preliminary
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

Pin Configurations(1,2,3,8) (con't.)

03/13/03

VDD

(4) A18L

A17L

A16L

A15L

A14L

A13L

A12L

A11L

A10L

A9L

A8L

A7L

UBL

LBL

CE1L

CE0L

VDD

VSS

SEML

OEL

WR/L

BUSYL

INTL

NC A6L

A5L

A4L

A3L

A2L

A1L

A0L

VDD

VSS

VDDQR

VSS

I/O9L

I/O9R

I/O10L

I/O10R

I/O11L

I/O11R

VDDQL

VSS

I/O12L

I/O12R

VDDQR

ZZR

VDD

VSS

VDDQL

VSS

I/O13R

I/O13L

I/O14R

I/O14L

VDDQR

VSS

I/O15R

I/O15L

I/O16R

I/O16L

I/O17R

I/O17L

VSS

VDDQL

35 36

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

70T633/1DD

DD-144(5,6,7)

144-Pin TQFP

Top View(8)

109

108

107

106

105

104

103

102

101

100

OPTL

VDDQR

VSS

I/O8L

I/O8R

I/O7L

I/O7R

I/O6L

I/O6R

VSS

VDDQL

I/O5L

I/O5R

VSS

VDDQR

VDD

VSS

ZZL

VDDQL

I/O4R

I/O4L

I/O3R

I/O3L

VSS

VDDQR

I/O2R

I/O2L

I/O1R

I/O1L

I/O0R

I/O0L

VSS

VDDQL

OPTR

VDD

NC NC A18R

A17R

A16R

A15R

A14R

A13R

A12R

A11R

A10R

A9R

A8R

A7R

UBR

LBR

CE1R

CE0R

(4)

NOTES:

VDD

VSS

SEMR

OER

WR BUSYR R/

INTR

SM/ A6R

A5R

A4R

A3R

A2R

A1R

A0R

VDD

VSS

5670 drw 02a

1.All VDD pins must be connected to 2.5V power supply.

2.All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is set to VSS (0V).

3.All VSS pins must be connected to ground.

4.A18X is a NC for IDT70T631.

5.Package body is approximately 20mm x 20mm x 1.4mm.

6.This package code is used to reference the package diagram.

7.8ns Commercial and 10ns Industrial speed grades are not available in the DD-144 package.

8.This text does not indicate orientation of the actual part-marking.

9.Due to the restricted number of pins, JTAG is not supported in the DD-144 package.

IDT70T633/1S	Preliminary
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

Pin Configurations(1,2,3)(con't.)

03/12/03

I/O9L

VSS

TDO

A16L

A12L

A8L

VDD

SEML

INTL

A4L

A0L

OPTL

VSS

TDI

A17L

A13L

A9L

CE0L

VSS

BUSYL

A5L

A1L

VSS

VDD QR

I/O8L

VDD QL

I/O9R

VDDQR

VDD

A18L

(4)

A14 L

A1 0L

UBL

CE1L

VSS

R/WL

A6L

A2L

VDD

I/O8R

VSS

I/O10L

A15 L

A11L

A7 L

LBL

VDD

OEL

A3L

VDD

VD DQL

I/O7L

I/O7 R

I/O11L

VD DQ R

I/O10 R

I/O6L

VSS

VDD QL

I/O11R

VSS

I/O6R

VD DQ R

VSS

I/O12L

VDD QL

I/O5L

70T633/1BF

VDD

VD DQ R

I/O12R

VD D

VSS

I/O5R

BF-208(5,6)

VDD QL

VD D

VSS

ZZR

208-Ball BGA

ZZL

VDD

VSS

VDDQ R

I/O14R

VSS

I/O13R

VSS

Top View

(7)

I/O3R

VD DQL

I/O4R

VSS

I/O14L

VD DQ R

I/O13L

I/O3L

VSS

I/O4L

VDD QL

I/O15R

VSS

I/O2R

VDDQ R

VSS

I/O15 L

I/O1R

VDD QL

I/O2L

I/O16R

I/O16L

VD DQ R

TRST

A16R

A12R

A8R

VD D

SEMR

INTR

A4R

I/O1L

VSS

I/O17 R

TCK

A17R

A13R

A9R

CE0R

VSS

BUSYR

A5R

A1R

VSS

VD DQ L

I/O0R

VDDQR

I/O17L

VD DQ L

TMS

A18R (4)

A14R

A1 0R

UBR

CE1R

VSS

R/WR

A6R

A2R

VS S

VSS

VDD

A15R

A11R

A7R

LBR

VDD

OER

M/S

A3R

A0R

VDD

OPTR

I/O0L

5670 drw 02b

NOTES:

1.All VDD pins must be connected to 2.5V power supply.

2.All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is set to VSS (0V).

3.All VSS pins must be connected to ground.

4.A18X is a NC for IDT70T631.

5.Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

6.This package code is used to reference the package diagram.

7.This text does not indicate orientation of the actual part-marking.

IDT70T633/1S	Preliminary
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

Pin Names

Left Port		Right Port	Names

CE0L, CE1L		CE0R, CE1R	Chip Enables (Input)

R/WL		R/WR	Read/Write Enable (Input)

OEL		OER	Output Enable (Input)

A0L - A18L(1)		A0R - A18R(1)	Address (Input)
I/O0L - I/O17L		I/O0R - I/O17R	Data Input/Output

SEML		SEMR	Semaphore Enable (Input)

INTL		INTR	Interrupt Flag (Output)

BUSYL		BUSYR	Busy Flag (Output)

UBL		UBR	Upper Byte Select (Input)

LBL		LBR	Lower Byte Select (Input)

VDDQL		VDDQR	Power (I/O Bus) (3.3V or 2.5V)(2) (Input)
OPTL		OPTR	Option for selecting VDDQX(2,3) (Input)
ZZL		ZZR	Sleep Mode Pin(4) (Input)
	M/S		Master or Slave Select (Input)(5)
	VDD		Power (2.5V)(2) (Input)
	VSS		Ground (0V) (Input)

	TDI		Test Data Input

	TDO		Test Data Output

	TCK		Test Logic Clock (10MHz) (Input)

	TMS		Test Mode Select (Input)

	TRST		Reset (Initialize TAP Controller) (Input)

			5670 tbl 01

NOTES:

1.Address A18x is a NC for IDT70T631.

2.VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on I/OX.

3.OPTX selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V.

4.The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected during sleep mode. It is recommended that boundry scan not be operated during sleep mode.

5.BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

IDT70T633/1S										Preliminary
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM									Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1)
								Upper Byte	Lower Byte
OE	SEM	CE0	CE1	UB	LB	R/W	ZZ	I/O9-17	I/O0-8	MODE
X	H	H	X	X	X	X	L	High-Z	High-Z	Deselected–Power Down

X	H	X	L	X	X	X	L	High-Z	High-Z	Deselected–Power Down

X	H	L	H	H	H	X	L	High-Z	High-Z	Both Bytes Deselected

X	H	L	H	H	L	L	L	High-Z	DIN	Write to Lower Byte

X	H	L	H	L	H	L	L	DIN	High-Z	Write to Upper Byte

X	H	L	H	L	L	L	L	DIN	DIN	Write to Both Bytes

L	H	L	H	H	L	H	L	High-Z	DOUT	Read Lower Byte

L	H	L	H	L	H	H	L	DOUT	High-Z	Read Upper Byte

L	H	L	H	L	L	H	L	DOUT	DOUT	Read Both Bytes

H	H	L	H	L	L	X	L	High-Z	High-Z	Outputs Disabled

X	X	X	X	X	X	X	H	High-Z	High-Z	High-Z Sleep Mode

										5670 tbl 02

NOTE:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

Truth Table II – Semaphore Read/Write Control(1)

			Inputs(1)				Outputs
CE(2)	R/W	OE		UB	LB	SEM	I/O1-17	I/O0	Mode
H	H	L		L	L	L	DATAOUT	DATAOUT	Read Data in Semaphore Flag(3)
H	↑	X		X	L	L	X	DATAIN	Write I/O0 into Semaphore Flag

L	X	X		X	X	L	______	______	Not Allowed
							______	______

NOTES:	5670 tbl 03

1.There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O17). These eight semaphore flags are addressed by A0-A2.

2.CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.

3.Each byte is controlled by the respective UB and LB. To read data UB and/or LB = VIL.

IDT70T633/1S	Preliminary
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

RecommendedOperating

Temperature and Supply Voltage(1)

	Ambient
Grade	Temperature	GND	VDD

Commercial	0OC to +70OC	0V	2.5V + 100mV
Industrial	-40OC to +85OC	0V	2.5V + 100mV

NOTE:	5670 tbl 04

1. This is the parameter TA. This is the "instant on" case temperature.

Absolute Maximum Ratings(1)

Symbol	Rating	Commercial	Unit
		& Industrial

VTERM	VDD Terminal Voltage	-0.5 to 3.6	V
(VDD)	with Respect to GND
VTERM(2)	VDDQ Terminal Voltage	-0.3 to VDDQ + 0.3	V
(VDDQ)	with Respect to GND
VTERM(2)	Input and I/O Terminal	-0.3 to VDDQ + 0.3	V
(INPUTS and I/O's)	Voltage with Respect to GND

TBIAS(3)	Temperature	-55 to +125	oC
	Under Bias
TSTG	Storage	-65 to +150	oC
	Temperature

TJN	Junction Temperature	+150	oC
IOUT(For VDDQ = 3.3V)	DC Output Current	50	mA

IOUT(For VDDQ = 2.5V)	DC Output Current	40	mA

5670 tbl 07

NOTES:

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed VDDQ during power supply ramp up.

3.Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.

Capacitance(1)

(TA = +25°C, F = 1.0MHZ) TQFP ONLY

Symbol	Parameter	Conditions(2)	Max.	Unit
CIN	Input Capacitance	VIN = 3dV	8	pF

COUT(3)	Output Capacitance	VOUT = 3dV	10.5	pF

NOTES:	5670 tbl 08

1.These parameters are determined by device characterization, but are not production tested.

2.3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V.

3.COUT also references CI/O.

Recommended DC Operating Conditions with VDDQ at 2.5V

Symbol	Parameter	Min.	Typ.	Max.		Unit

VDD	Core Supply Voltage	2.4	2.5	2.6		V

VDDQ	I/O Supply Voltage(3)	2.4	2.5	2.6		V
VSS	Ground	0	0	0		V

	Input High Volltage	1.7		VDDQ + 100mV(2)		V
VIH	(Address, Control &	1.7	____	VDDQ + 100mV(2)		V
	Data I/O Inputs)(3)
VIH	Input High Voltage _	1.7	____	VDD + 100mV(2)		V
	JTAG
VIH	Input High Voltage -	VDD - 0.2V	____	VDD + 100mV(2)		V
	ZZ, OPT, M/S
VIL	Input Low Voltage	-0.3(1)	____	0.7		V
VIL	Input Low Voltage -	-0.3(1)	____	0.2		V
	ZZ, OPT, M/S
					5670 tbl 05

NOTES:

1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.

2.VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is less.

3.To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VSS (0V), and VDDQX for that port must be supplied as indicated above.

Recommended DC Operating Conditions with VDDQ at 3.3V

Symbol	Parameter	Min.	Typ.	Max.	Unit

VDD	Core Supply Voltage	2.4	2.5	2.6	V

VDDQ	I/O Supply Voltage(3)	3.15	3.3	3.45	V
VSS	Ground	0	0	0	V

	Input High Voltage	2.0		VDDQ + 150mV(2)	V
VIH	(Address, Control	2.0	____	VDDQ + 150mV(2)	V
	&Data I/O Inputs)(3)
VIH	Input High Voltage _	1.7	____	VDD + 100mV(2)	V
	JTAG
VIH	Input High Voltage -	VDD - 0.2V	____	VDD + 100mV(2)	V
	ZZ, OPT, M/S
VIL	Input Low Voltage	-0.3(1)	____	0.8	V
VIL	Input Low Voltage -	-0.3(1)	____	0.2	V
	ZZ, OPT, M/S
				5670 tbl 06

NOTES:

1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.

2.VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is less.

3.To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied as indicated above.

IDT70T633/1S	Preliminary
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)

			70T633/1S

Symbol	Parameter	Test Conditions	Min.	Max.	Unit

\|ILI\|	Input Leakage Current(1)	VDDQ = Max., VIN = 0V to VDDQ	___	10	µA
\|ILI\|	JTAG & ZZ Input Leakage Current(1,2)	VDD = Max., VIN = 0V to VDD	___	+30	µA
\|ILO\|	Output Leakage Current(1,3)	CE0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ	___	10	µA
VOL (3.3V)	Output Low Voltage(1)	IOL = +4mA, VDDQ = Min.	___	0.4	V
VOH (3.3V)	Output High Voltage(1)	IOH = -4mA, VDDQ = Min.	2.4	___	V
VOL (2.5V)	Output Low Voltage(1)	IOL = +2mA, VDDQ = Min.	___	0.4	V
VOH (2.5V)	Output High Voltage(1)	IOH = -2mA, VDDQ = Min.	2.0	___	V
NOTES:					5670 tbl 09

1.VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 6 for details.

2.Applicable only for TMS, TDI and TRST inputs.

3.Outputs tested in tri-state mode.

DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(VDD = 2.5V ± 100mV)

70T633/1S8(6)

70T633/1S10

70T633/1S12

70T633/1S15

Com'l Only

Com'l

Com'l Only

& Ind(6)

& Ind

Symbol

Parameter

Test Condition

Version

Typ.(4)

Max.

Typ.(4)

Max.

Typ.(4)

Max.

Typ.(4)

Max.

Unit

IDD

Dynamic Operating

CEL and CER= VIL,

COM'L

350

475

300

405

300

355

225

305

Current (Both

Outputs Disabled

IND

300

445

300

395

Ports Active)

f = fMAX(1)

____

ISB1(6)

Standby Current

CEL = CER = VIH

COM'L

115

140

120

105

(Both Ports - TTL

f = fMAX(1)

IND

145

130

Level Inputs)

____

ISB2(6)

Standby Current

CE"A" = VIL and CE"B" = VIH(5)

COM'L

240

315

200

265

180

230

150

200

(One Port - TTL

Active Port Outputs Disabled,

IND

200

290

180

255

Level Inputs)

f = fMAX(1)

____

ISB3

Full Standby Current

Both Ports CEL and

COM'L

(Both Ports - CMOS

CER > VDD - 0.2V, VIN > VDD - 0.2V

IND

Level Inputs)

or VIN < 0.2V, f = 0(2)

____

ISB4(6)

Full Standby Current

CE"A" < 0.2V and CE"B" > VDD - 0.2V(5)

COM'L

240

315

200

265

180

230

150

200

(One Port - CMOS

VIN > VDD - 0.2V or VIN < 0.2V, Active

IND

200

290

180

255

Level Inputs)

Port, Outputs Disabled, f = fMAX(1)

____

IZZ

Sleep Mode Current

ZZL = ZZR = VIH

COM'L

(Both Ports - TTL

f = fMAX(1)

IND

____

Level Inputs)

NOTES:

5670 tbl 10

1.At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS".

2.f = 0 means no address or control lines change. Applies only to input at CMOS level standby.

3. VDD = 2.5V, TA = 25°C for Typ. values, and are not production tested. IDD DC(f=0) = 100mA (Typ).

4.CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL

CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQX - 0.2V

CEX > VDDQX - 0.2V means CE0X > VDDQX - 0.2V or CE1X - 0.2V "X" represents "L" for left port or "R" for right port.

5.ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and /or ZZR = VIH.

6.8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

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