Integrated Device Technology Inc IDT70V05L25G, IDT70V05L25J, IDT70V05L25PF, IDT70V05L35G, IDT70V05L35J Datasheet

HIGH-SPEED 3.3V	IDT70V05S/L
8K x 8 DUAL-PORT
STATIC RAM

Integrated Device Technology, Inc.

FEATURES:

•True Dual-Ported memory cells which allow simultaneous access of the same memory location

•High-speed access

—Commercial: 25/35/55ns (max.)

•Low-power operation

—IDT70V05S

Active: 350mW (typ.) Standby: 3.5mW (typ.)

—IDT70V05L

Active: 350mW (typ.) Standby: 1mW (typ.)

•IDT70V05 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device

•M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave

•Busy and Interrupt Flags

•On-chip port arbitration logic

•Full on-chip hardware support of semaphore signaling between ports

•Fully asynchronous operation from either port

•Devices are capable of withstanding greater than 2001V electrostatic discharge

•Battery backup operation—2V data retention

•LVTTL-compatible, single 3.3V (±0.3V) power supply

•Available in 68-pin PGA, 68-pin PLCC, and a 64-pin TQFP

DESCRIPTION:

The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM. The IDT70V05 is designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE DualPort RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full-speed, error-free

FUNCTIONAL BLOCK DIAGRAM

OEL

CEL

R/WL

I/O0L- I/O7L

(1,2)

BUSYL

A12L

A0L

NOTES:

1.(MASTER): BUSY is output; (SLAVE): BUSY is input.

2.BUSY outputs and INT outputs

SEML are non-tri- (2)

stated push-pull. INTL

I/O

I/O

Control

Control

	Address	MEMORY	Address
	Decoder	ARRAY	Decoder
		13	13
		ARBITRATION
	CEL	INTERRUPT	CER
	OEL	SEMAPHORE	OER
		LOGIC
	R/WL		R/WR

M/S

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

OER

CER

R/WR

I/O0R-I/O7R

(1,2)

BUSYR

A12R

A0R

SEMR

INTR(2)

2941 drw 01

	COMMERCIAL TEMPERATURE RANGE		OCTOBER 1996
	©1996 Integrated Device Technology, Inc.	For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.	DSC-2941/3
		6.35
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IDT70V05S/L
HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM	COMMERCIAL TEMPERATURE RANGE

operation without the need for additional discrete logic. This device provides two independent ports with separate

control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 350mW of power. Low-power (L) versions offer battery backup data retention capability with typical power consumption of 500μW from a 2V battery.

The IDT70V05 is packaged in a ceramic 68-pin PGA, a 68pin PLCC, and a 64-pin thin plastic quad flatpack (TQFP).

PIN CONFIGURATIONS (1,2)

INDEX					I/O1L			I/O0L			N/C OEL						R/WL			SEML			CEL			N/C			N/C			VCC A12L						A11L			A10L			A9L			A8L A7L						A6L
I/O2L			9				8			7					6		5			4			3			2			1			68 67 66 65 64															63 62 61											A5L
			10																																																		60
I/O3L			11																																																		59					A4L
I/O4L			12																																																		58					A3L
I/O5L			13																																																		57					A2L
GND			14																					IDT70V05																													56					A1L
I/O6L			15																																																		55					A0L
																										J68-1
I/O7L			16																							F68-1																											54					INT
VCC																																																					53					L
			17																																																							BUSYL
GND			18																PLCC / FLATPACK																																		52					GND
I/O0R			19																			TOP VIEW(3)																															51					M/S
I/O1R			20																																																		50					BUSY
I/O2R																																																					49					R
			21																																																							INTR
VCC			22																																																		48					A0R
I/O3R			23																																																		47					A1R
I/O4R			24																																																		46					A2R
I/O5R			25																																																		45					A3R
I/O6R			26																																																		44					A4R
			27				28 29						30 31							32 33 34 35												36 37 38 39												40 41 42 43
			I/O7R N/C ROE R/WR												SEMR CER N/C N/C														GND			A12R A11R						A10R			A9R			A8R A7R A6R									A5R			2941 drw 02

INDEX

I/O2L

I/O3L

I/O4L

I/O5L

GND

I/O6L

I/O7L

VCC

GND

I/O0R

I/O1R

I/O2R

VCC

I/O3R

I/O4R

I/O5R

NOTES:

1.All Vcc pins must be connected to the power supply.

2.All GND pins must be connected to the ground supply.

3.This text does not indicate orientation of the actual part-marking.

	I/O1L
1	64
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16	17
I/O6R

I/O0L		OEL		R/WL		SEM L		CEL		N/C		VCC		A12L		A11L		A10L		A9L		A8L
63		62		61		60		59		58		57		56		55		54		53		52

IDT70V05

PN-64

TQFP

TOP VIEW(3)

18	19		20		21		22		23		24		25		26		27		28		29
I/O7R	OER		R/WR		SEMR		CER		N/C		GND			A12R		A11R	A10R		A9R		A8R

51 A7L

A7R 30

A6L		A5L
50		49		48
				47
				46
				45
				44
				43
				42
				41
				40
				39
				38
				37
				36
				35
				34
31		32		33
	A6R		A5R

A4L

A3L

A2L

A1L

A0L

INTL

BUSYL

GND

M/S

BUSYR

INTR

A0R

A1R

A2R

A3R

A4R

2941 drw 03

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IDT70V05S/L
HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM													COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CONT'D) (1,2)
11				51	50		48	46	44	42	40	38	36
				A5L	A4L		A2L	A0L	BUSYL	M/S	INTR	A1R	A3R
10		53		52	49		47	45	43	41	39	37	35		34
		A7L		A6L	A3L		A1L	INTL	GND	BUSYR	A0R	A2R	A4R		A5R
09		55		54									32		33
		A9L		A8L									A7R		A6R
08		57		56									30		31
		A11L		A10L									A9R		A8R
07		59		58									28		29
		VCC		A12L				IDT70V05					A11R		A10R
								G68-1
06		61		60									26		27
		N/C		N/C				68-PIN PGA					GND		A12R
05		63		62				TOP VIEW(3)					24		25
		SEML		CEL									N/C		N/C
04		65		64									22		23
		OE	L	R/WL									SEMR		CE	R
03		67		66									20		21
		I/O0L		N/C									OE	R	R/WR
02		68		1	3		5	7	9	11	13	15	18		19
		I/O1L		I/O2L	I/O4L		GND	I/O7L	GND	I/O1R	VCC	I/O4R	I/O7R		N/C
01				2	4		6	8	10	12	14	16	17
				I/O3L	I/O5L		I/O6L	VCC	I/O0R	I/O2R	I/O3R	I/O5R	I/O6R
		A		B	C		D	E	F	G	H	J	K		L
INDEX
															2941 drw 04

NOTES:

1.All VCC pins must be connected to power supply.

2.All GND pins must be connected to ground supply.

3.This text does not indicate oriention of the actual part-marking

PIN NAMES

Left Port		Right Port	Names
CEL		CER	Chip Enable
R/WL		R/WR	Read/Write Enable
OEL		OER	Output Enable
A0L – A12L		A0R – A12R	Address
I/O0L – I/O7L		I/O0R – I/O7R	Data Input/Output
SEML		SEMR	Semaphore Enable
INTL		INTR	Interrupt Flag
BUSYL		BUSYR	Busy Flag
	M/S		Master or Slave Select
	VCC		Power
	GND		Ground
			2941 tbl 01

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IDT70V05S/L
HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM	COMMERCIAL TEMPERATURE RANGE

TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL

	Inputs(1)			Outputs
CE	R/W	OE	SEM	I/O0-7	Mode
H	X	X	H	High-Z	Deselected: Power Down
L	L	X	H	DATAIN	Write to Memory
L	H	L	H	DATAOUT	Read Memory
X	X	H	X	High-Z	Outputs Disabled
NOTE:					2941 tbl 02
1. A0L — A12L ¹ A0R — A12R.
					(1)
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL
	Inputs			Outputs
CE	R/W	OE	SEM	I/O0-7	Mode
H	H	L	L	DATAOUT	Read Data in Semaphore Flag
H		X	L	DATAIN	Write DIN0 into Semaphore Flag
L	X	X	L	—	Not Allowed
NOTE:					2941 tbl 03

1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.

ABSOLUTE MAXIMUM RATINGS(1)

Symbol	Rating	Commercial	Unit
VTERM(2)	Terminal Voltage	–0.5 to +4.6	V
	with Respect
	to GND
TA	Operating	0 to +70	°C
	Temperature
TBIAS	Temperature	–55 to +125	°C
	Under Bias
TSTG	Storage	–55 to +125	°C
	Temperature
IOUT	DC Output	50	mA
	Current
NOTES:		2941 tbl 04

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.VTERM must not exceed Vcc + 0.3V.

RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE

	Ambient
Grade	Temperature	GND	VCC
Commercial	0°C to +70°C	0V	3.3V ± 0.3V

2941 tbl 05

RECOMMENDED DC OPERATING

CONDITIONS

Symbol	Parameter	Min.	Typ.	Max.	Unit
VCC	Supply Voltage	3.0	3.3	3.6	V
GND	Supply Voltage	0	0	0	V
VIH	Input High Voltage	2.0	—	Vcc+0.3	V
VIL	Input Low Voltage	-0.3(1)	—	0.8	V
NOTES:				2941 tbl 06

1.VIL³ -1.5V for pulse width less than 10ns.

2.VTERM must not exceed Vcc + 0.5V.

CAPACITANCE(1)

(TA = +25°C, f = 1.0MHz)TQFP ONLY

Symbol	Parameter	Conditions(1)	Max.		Unit
CIN	Input Capacitance	VIN = 3dV	11		pF
COUT	Output	VOUT = 3dV	11		pF
	Capacitance
NOTES:				2941 tbl 07

1.This parameter is determined by device characterization but is not production tested.

2.3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.

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IDT70V05S/L
HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM	COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 3.3V ± 0.3V)

			IDT70V05S		IDT70V05L
Symbol	Parameter	Test Conditions	Min.	Max.	Min.	Max.	Unit
|ILI|	Input Leakage Current(1)	VCC = 3.6V, VIN = 0V to VCC	—	10	—	5	mA
|ILO|	Output Leakage Current	CE = VIH, VOUT = 0V to VCC	—	10	—	5	mA
VOL	Output Low Voltage	IOL = 4mA	—	0.4	—	0.4	V
VOH	Output High Voltage	IOH = -4mA	2.4	—	2.4	—	V
NOTE:							2941 tbl 08

1. At Vcc ≤ 2.0V input leakages are undefined.

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)							(VCC = 3.3V ± 0.3V)
						70V05X25			70V05X35		70V05X55
		Test
Symbol	Parameter	Condition	Version			Typ.(2) Max.			Typ.(2)	Max.	Typ.(2)		Max.		Unit
ICC	Dynamic Operating	CE = VIL, Outputs Open	COM’L		S	80		140	70	115	70		115		mA
	Current	SEM = VIH			L	70		120	60	100	60		100
	(Both Ports Active)	f = fMAX(3)
ISB1	Standby Current	CER = CEL = VIH	COM’L.		S	12		25	10	25	10		25		mA
	(Both Ports — TTL	SEMR = SEML = VIH			L	10		20	8	20	8		20
	Level Inputs)	f = fMAX(3)
ISB2	Standby Current	CEL or CER = VIH	COM’L.		S	40		82	35	72	35		72		mA
	(One Port — TTL	Active Port Outputs Open			L	30		72	25	62	25		62
	Level Inputs)	f = fMAX(3)
		SEMR = SEML = VIH
ISB3	Full Standby Current	Both Ports CEL and	COM’L.		S	1.0		5	1.0	5	1.0		5		mA
	(Both Ports — All	CER ³ VCC - 0.2V			L	0.2		2.5	0.2	2.5	0.2		2.5
	CMOS Level Inputs)	VIN ³ VCC - 0.2V or
		VIN £ 0.2V, f = 0(4)
		SEMR = SEML ³ VCC - 0.2V
ISB4	Full Standby Current	One Port CEL or	COM’L.		S	50		81	45	71	45		71		mA
	(One Port — All	CER ³ VCC - 0.2V			L	40		71	35	61	35		61
	CMOS Level Inputs)	SEMR = SEML ³ VCC - 0.2V
		VIN ³ VCC - 0.2V or VIN £ 0.2V
		Active Port Outputs Open
		f = fMAX(3)
NOTES:														2941 tbl 09

1."X" in part numbers indicates power rating (S or L).

2.VCC = 3.3V, TA = +25°C.

3.At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.

4.f = 0 means no address or control lines change.

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IDT70V05S/L
HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM	COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS

Input Pulse Levels	GND to 3.0V
Input Rise/Fall Times	5ns Max.
Input Timing Reference Levels	1.5V
Output Reference Levels	1.5V
Output Load	Figures 1and 2

3.3V	3.3V
590Ω	590Ω

DATAOUT

BUSY			DATAOUT
INT	435Ω	30pF	435Ω	5pF

2941 tbl 10

2941 drw 05

2941 drw 06

Figure 1. AC Output Test Load	Figure 2. Output Load
	(For tLZ, tHZ, tWZ, tOW)
	Including scope and jig.

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)

		IDT70V05X25		IDT70V05X35		IDT70V05X55
Symbol	Parameter	Min.	Max.	Min.	Max.	Min.	Max.		Unit
READ CYCLE
tRC	Read Cycle Time	25	—	35	—	55	—		ns
tAA	Address Access Time	—	25	—	35	—	55		ns
tACE	Chip Enable Access Time(3)	—	25	—	35	—	55		ns
tAOE	Output Enable Access Time	—	15	—	20	—	30		ns
tOH	Output Hold from Address Change	3	—	3	—	3	—		ns
tLZ	Output Low-Z Time(1, 2)	3	—	3	—	3	—		ns
tHZ	Output High-Z Time(1, 2)	—	15	—	20	—	25		ns
tPU	Chip Enable to Power Up Time(2)	0	—	0	—	0	—		ns
tPD	Chip Disable to Power Down Time(2)	—	25	—	35	—	50		ns
tSOP	Semaphore Flag Update Pulse (OE or SEM)	15	—	15	—	15	—		ns
tSAA	Semaphore Address Access Time	—	35	—	45	—	65		ns
NOTES:								2941 tbl 11

1.Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2.This parameter is guaranteed by device characterization but not production tested.

3.To access RAM, CE = VIL, SEM = VIH.

4."X" in part numbers indicates power rating (S or L).

TIMING OF POWER-UP POWER-DOWN

CE

ICC

tPU

tPD

50%

50%

ISB

2941 drw 07

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