Integrated Device Technology Inc IDT6178S10Y, IDT6178S12D, IDT6178S12DB, IDT6178S12P, IDT6178S12PB Datasheet

	IDT6178S
	CMOS StaticRAM	16K					(4K x 4-BIT) CACHE	-TAG RAM		MILITARY AND COMMERCIAL TEMPERATURE RANGE
									CMOS StaticRAM	IDT6178S
									16K (4K x 4-BIT)
									CACHE-TAG RAM
	Integrated Device Technology, Inc.
FEATURES:									DESCRIPTION:

•High-speed Address to MATCH Valid time

–Military: 12/15/20/25ns

–Commercial: 10/12/15/20/25ns (max.)

•High-speed Address Access time

–Military: 12/15/20/25ns

–Commercial: 10/12/15/20/25ns (max.)

•Low-power consumption

–IDT6178S

Active: 300mW (typ.)

•Produced with advanced CMOS high-performance technology

•Input and output TTL-compatible

•Standard 22-pin Plastic or Ceramic DIP, 24-pin SOJ

•Military product 100% compliant to MIL-STD-883, Class B

The IDT6178 is a high-speed cache address comparator sub-system consisting of a 16,384-bit StaticRAM organized as 4K x 4. Cycle Time and Address to MATCH Valid are equal. The IDT6178 features an onboard 4-bit comparator that compares RAM contents and current input data. The result is an active HIGH on the MATCH pin. The MATCH pins of several IDT6178s can be handed together to provide enabling or acknowledging signals to the data cache or processor.

The IDT6178 is fabricated using IDT’s high-performance, high-reliability CMOS technology. Address to MATCH and Data to MATCH times are as fast as 10ns.

All inputs and outputs of the IDT6178 are TTL-compatible and the device operates from a single 5V supply.

The IDT6178 is packaged in either a 22-pin, 300-mil Plastic or Ceramic DIP package or 24-pin SOJ. Military grade product is manufactured in compliance with latest revision of MIL- STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.

FUNCTIONAL BLOCK DIAGRAM

A0

ADDRESS

DECODE

A11

4

I/O0 – I/O3

4

WE

OE

CONTROL

CLR

4

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

16,384-BIT	VCC
MEMORY
ARRAY	GND

CONTROL I/O

CLEAR

MEMORY

ARRAY

4

COMPARATOR

MATCH

2953 drw 01

MILITARY AND COMMERCIAL TEMPERATURE RANGES	MAY 1994
©1994 Integrated Device Technology, Inc.	DSC-1059/2

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IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM	MILITARY AND COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS

A0		1		22		VCC
A1		2		21		A11
		3		20		A10
A2
				19		A9
A3		4
				18		A8
A4		5	P22-1
		6	&	17		CLR
A5
			D22-1	16		I/O3
A6		7
				15		I/O2
A7		8
OE		9		14		I/O1
		10		13		I/O0
WE
				12		MATCH
GND		11

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DIP

TOP VIEW

PIN DESCRIPTIONS

A0–A11	Address Inputs
I/O0–I/O3	Data Input/Output
MATCH	Match
WE	Write Enable
OE	Output Enable
CLR	Clear
VCC	Power
GND	Ground

2953 tbl 01

	A0	1		24			VCC
	A1	2		23			A11
	A2	3		22			A10
	A3	4		21			A9
	A4	5		20			A8
	A5	6	S024-4	19			NC
	NC	7		18			CLR
	A6	8		17			I/O3
	A7	9		16			I/O2
	OE	10		15			I/O1
	WE	11		14			I/O0
	GND	12		13			MATCH
							2953 drw 03
			SOJ
			TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol		Rating					Value		Unit
VTERM	Terminal Voltage with respect						–0.5 to +7.0		V
	to GND
TA	Operating Temperature					–55 to +125			°C
TBIAS	Temperature Under Bias					–65 to +135			°C
TSTG	Storage Temperature					–65 to +150			°C
PT	Power Dissipation					1.0			W
IOUT	DC Output Current					50			mA
NOTE:								2953 tbl 04

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty.

RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE

Grade	Ambient Temperature	GND	VCC
Commercial	0°C to +70°C	0V	5.0V ± 10%
Military	–55°C to +125°C	0V	5.0V ± 10%
			2953 tbl 02

TRUTH TABLES(1)

WE	OE	CLR	MATCH	Mode
H	H	H	Valid(2)	Match Cycle
L	X	H	Invalid	Write Cycle
H	L	H	Invalid	Read Cycle
X	X	L	Invalid	Clear Cycle
NOTE:				2953 tbl 03

1.H = VIH, L = VIL, X = Don’t care.

2.Valid Match = VOH, Valid Non-Match = VOL.

RECOMMENDED DC

OPERATING CONDITIONS

Symbol	Parameter	Min.	Typ.	Max.	Unit
VCC	Supply Voltage	4.5	5.0	5.5	V
GND	Supply Voltage	0	0	0	V
VIH	Input High Voltage	2.2(2)	–	6.0	V
VIL	Input Low Voltage	–0.5(1)	–	0.8	V
NOTES:					2953 tbl 05

1.VIL = –3.0V for pulse width less than 20ns, once per cycle.

2.VIH = 2.5V for clear pin.

CAPACITANCE (TA = 25°C, f = 1MHz)

Symbol	Parameter	Condition	Max	Units
CIN	Input Capacitance	VIN = 0V	8	pF
CI/O	I/O Capacitance	VOUT = 0V	8	pF
NOTE:				2953 tbl 06

1.This parameter is determined by device characterization, but is not production tested.

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IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM	MILITARY AND COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)

							6178S
Symbol		Parameter		Test Condition			Min.			Max.	Unit
|ILI|		Input Leakage Current	VCC = 5.5V, VIN = 0V to VCC				—			10	μA
|ILO|		Output Leakage Current	OE = VIH, VOUT = 0V to VCC				—			10	μA
VOL		Output Low Voltage	IOL = 8mA (I/O0 – I/O3)				—			0.4	V
			IOL = 10mA (I/O0 – I/O3)				—			0.5	V
			IOL = 16mA (Match)				—			0.4	V
			IOL = 20mA (Match)				—			0.5	V
VOH		Output High Voltage	IOH = –4mA (I/O0 – I/O3)				2.4			—	V
			IOH = –8mA (Match)				2.4			—	V
DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)											2953 tbl 07
				6178S10		6178S12(1)	6178S15(1)			6178S20/25
Symbol		Parameter		Max.		Max.	Max.			Max.	Unit
ICC1	Operating Power Supply Current		COM'L.	90		90	90			90	mA
	Outputs Open, VCC = Max., f = 0(2)		MIL.	—		110	110			110	mA
ICC2	Dynamic Operating Current		COM'L.	180		160	140			140	mA
	Outputs Open, VCC = Max., f = fMAX(2)		MIL.	—		180	160			160	mA
NOTES:											2953 tbl 08

1.Military values are preliminary only.

2.fMAX = 1/tRC, only address inputs are cycling at fMAX. f = 0 means no address inputs change.

AC TEST CONDITIONS				+5V
Input Pulse Levels	GND to 3.0V
				240Ω
Input Rise/Fall Times	5ns
Input Timing Reference Levels	1.5V
			MATCHOUT
Output Reference Levels	1.5V
AC Test Load	See Figures 2 and 3		128Ω	30pF*
AC Test Load for Match Cycle	See Figure 1
	2953 tbl 09

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Figure 1. AC Test Load for MATCH

+5V

+5V

	480Ω		480Ω
DATAOUT		DATAOUT
255Ω	30pF*	255Ω	5pF*
	2953 drw 05		2953 drw 06
Figure 2. AC Test Load		Figure 3. AC Test Load

(for tOLZ, tOHZ, tWHZ, tOW)

* Including scope and jig.

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