IDT54/74FCT821AT/BIDT54FCT821ATD/CT, 823/825AT/BT/CT/DT |
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MILITARY AND COMMERCIAL TEMPERATURE RANGES |
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HIGH-PERFORMANCE |
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CMOS BUS INTERFACE REGISTERS |
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HIGH-PERFORMANCE |
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IDT54/74FCT821AT/BT/CT |
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CMOS BUS |
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IDT54/74FCT823AT/BT/CT/DT |
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INTERFACE REGISTERS |
IDT54/74FCT825AT/BT/CT |
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Integrated Device Technology, Inc.
FEATURES:
•Common features:
–Low input and output leakage ≤1μA (max.)
–CMOS power levels
–True TTL input and output compatibility
–VOH = 3.3V (typ.)
–VOL = 0.3V (typ.)
–Meets or exceeds JEDEC standard 18 specifications
–Product available in Radiation Tolerant and Radiation Enhanced versions
–Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked)
–Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages
•Features for FCT821T/FCT823T/FCT825T:
–A, B, C and D speed grades
–High drive outputs (-15mA IOH, 48mA IOL)
–Power off disable outputs permit “live insertion”
DESCRIPTION:
The FCT82xT series is built using an advanced dual metal CMOS technology. The FCT82xT series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The FCT821T are buffered, 10-bit wide versions of the popular FCT374T function. The FCT823T are 9-bit wide buffered registers with Clock Enable (EN) and Clear (CLR) – ideal for parity bus interfacing in high-performance microprogrammed systems. The FCT825T are 8-bit buffered registers with all the FCT823T controls plus multiple enables (OE1, OE2, OE3) to allow multiuser control of the interface, e.g., CS, DMA and RD/WR. They are ideal for use as an output port requiring high IOL/IOH.
The FCT82xT high-performance interface family can drive large capacitive loads, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D0 |
DN |
EN
CLR |
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D CL Q |
D CL Q |
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CP Q |
CP Q |
CP |
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OE |
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Y0 |
YN |
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2567 drw 01 |
The IDT logo is a registered trademark of Integrated Device Technology, Inc. |
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MILITARY AND COMMERCIAL TEMPERATURE RANGES |
AUGUST 1995 |
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©1995 Integrated Device Technology, Inc |
6.21 |
DSC-4202/5 |
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6.21 |
1 |
1
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
PIN CONFIGURATIONS
FCT821 10-BIT REGISTER
OE |
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1 |
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24 |
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VCC |
D0 |
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2 |
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23 |
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Y0 |
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D1 |
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3 |
P24-1 |
22 |
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Y1 |
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D2 |
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4 |
21 |
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Y2 |
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D3 |
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5 |
D24-1 |
20 |
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Y3 |
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D4 |
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6 |
SO24-2 19 |
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Y4 |
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D5 |
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7 |
SO24-7 18 |
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Y5 |
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D6 |
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8 |
SO24-8 17 |
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Y6 |
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D7 |
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9 |
& |
16 |
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Y7 |
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E24-1 |
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D8 |
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Y8 |
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10 |
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15 |
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D9 |
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11 |
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14 |
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Y9 |
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GND |
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12 |
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13 |
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CP |
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DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
FCT823 9-BIT REGISTER
OE |
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1 |
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24 |
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VCC |
D0 |
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2 |
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23 |
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Y0 |
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D1 |
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3 |
P24-1 |
22 |
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Y1 |
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D2 |
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4 |
21 |
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Y2 |
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D3 |
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5 |
D24-1 |
20 |
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Y3 |
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D4 |
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6 |
SO24-2 |
19 |
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Y4 |
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SO24-7 |
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18 |
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D5 |
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7 |
SO24-8 |
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Y5 |
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D6 |
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8 |
17 |
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Y6 |
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& |
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D7 |
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9 |
16 |
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Y7 |
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E24-1 |
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D8 |
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10 |
15 |
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Y8 |
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CLR |
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11 |
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14 |
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EN |
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GND |
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12 |
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13 |
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CP |
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DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
FCT825 8-BIT REGISTER
OE1 |
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1 |
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24 |
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VCC |
OE2 |
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2 |
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23 |
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OE3 |
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D0 |
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3 |
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22 |
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Y0 |
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D1 |
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4 |
P24-1 |
21 |
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Y1 |
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D2 |
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5 |
D24-1 |
20 |
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Y2 |
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D3 |
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6 |
SO24-2 19 |
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Y3 |
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D4 |
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7 |
SO24-8 18 |
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Y4 |
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D5 |
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8 |
& |
17 |
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Y5 |
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D6 |
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9 |
E24-1 |
16 |
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Y6 |
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D7 |
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10 |
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15 |
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Y7 |
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CLR |
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11 |
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14 |
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EN |
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GND |
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12 |
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13 |
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CP |
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DIP/SOIC/QSOP/CERPACK
TOP VIEW
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INDEX |
D1 |
D0 |
OE NC VCC Y0 Y1 |
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D2 |
4 |
3 |
2 |
1 28 27 26 |
Y2 |
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5 |
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25 |
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D3 |
6 |
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24 |
Y3 |
D4 |
7 |
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23 |
Y4 |
NC |
8 |
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L28-1 |
22 |
NC |
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D5 |
9 |
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21 |
Y5 |
D6 |
10 |
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20 |
Y6 |
D7 |
11 |
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19 |
Y7 |
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1213 14 15 16 17 18 |
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D8 |
D9 |
GND |
NC CP Y9 |
Y8 |
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LCC |
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TOP VIEW |
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INDEX |
D1 D0 |
OE NC |
VCC Y0 Y1 |
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D2 |
4 |
3 |
2 |
1 |
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Y2 |
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5 |
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D3 |
6 |
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24 |
Y3 |
D4 |
7 |
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23 |
Y4 |
NC |
8 |
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L28-1 |
22 |
NC |
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D5 |
9 |
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21 |
Y5 |
D6 |
10 |
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20 |
Y6 |
D7 |
11 |
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19 |
Y7 |
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1213 14 15 16 17 18 |
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D8 |
CLR |
GND |
NC |
CP EN |
Y8 |
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LCC |
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TOP VIEW |
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INDEX |
D0 |
OE2 |
OE1 |
NC |
VCC OE3 |
Y0 |
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D1 |
4 |
3 |
2 |
1 |
28 27 26 |
Y1 |
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5 |
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25 |
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D2 |
6 |
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24 |
Y2 |
D3 |
7 |
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23 |
Y3 |
NC |
8 |
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L28-1 |
22 |
NC |
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D4 |
9 |
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21 |
Y4 |
D5 |
10 |
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20 |
Y5 |
D6 |
11 |
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19 |
Y6 |
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1213 14 15 16 17 18 |
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D7 |
CLR |
GND |
NC |
CP EN Y7 |
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LCC |
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TOP VIEW |
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2567 drw 02
2567 drw 03
2567 drw 04
6.21 |
2 |
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT |
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HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
PIN DESCRIPTION
Names |
I/O |
Description |
DI |
I |
The D flip-flop data inputs. |
CLR |
I |
When the clear input is LOW and OE is |
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LOW, the QI outputs are LOW. When |
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the clear input is HIGH, data can be |
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entered into the register. |
CP |
I |
Clock Pulse for the Register; enters |
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data into the register on the LOW-to- |
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HIGH transition. |
YI |
O |
The register 3-state outputs. |
EN |
I |
Clock Enable. When the clock enable is |
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LOW, data on the D I input is transferred |
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to the QI output on the LOW-to-HIGH |
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clock transition. When the clock enable |
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is HIGH, the QI outputs do not change |
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state, regardless of the data or clock |
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input transitions. |
OE |
I |
Output Control. When the OE input is |
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HIGH, the Y I outputs are in the high- |
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impedance state. When the OE input is |
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LOW, the TRUE register data is present |
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at the YI outputs. |
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2567 tbl 01 |
FUNCTION TABLE(1)
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Inputs |
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Internal/ |
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Outputs |
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OE |
CLR |
EN |
DI |
CP |
QI |
YI |
Function |
H |
H |
L |
L |
− |
L |
Z |
High Z |
H |
H |
L |
H |
− |
H |
Z |
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H |
L |
X |
X |
X |
L |
Z |
Clear |
L |
L |
X |
X |
X |
L |
L |
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H |
H |
H |
X |
X |
NC |
Z |
Hold |
L |
H |
H |
X |
X |
NC |
NC |
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H |
H |
L |
L |
− |
L |
Z |
Load |
H |
H |
L |
H |
− |
H |
Z |
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L |
H |
L |
L |
− |
L |
L |
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L |
H |
L |
H |
− |
H |
H |
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NOTE: |
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2567 tbl 02 |
1.H = HIGH L = LOW
X = Don’t Care
NC = No Change
− = LOW-to-HIGH Transition Z = High Impedance
ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Rating |
Commercial |
Military |
Unit |
VTERM(2) |
Terminal Voltage |
–0.5 to +7.0 |
–0.5 to +7.0 |
V |
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with Respect to |
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GND |
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VTERM(3) |
Terminal Voltage |
–0.5 to |
–0.5 to |
V |
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with Respect to |
VCC +0.5 |
VCC +0.5 |
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GND |
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TA |
Operating |
0 to +70 |
–55 to +125 |
°C |
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Temperature |
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TBIAS |
Temperature |
–55 to +125 |
–65 to +135 |
°C |
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Under Bias |
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TSTG |
Storage |
–55 to +125 |
–65 to +150 |
°C |
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Temperature |
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PT |
Power Dissipation |
0.5 |
0.5 |
W |
IOUT |
DC Output |
–60 to +120 |
–60 to +120 |
mA |
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Current |
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NOTES: |
2567 lnk 03 |
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1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted.
2.Input and VCC terminals only.
3.Outputs and I/O terminals only.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol |
Parameter(1) |
Conditions |
Typ. |
Max. |
Unit |
CIN |
Input |
VIN = 0V |
6 |
10 |
pF |
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Capacitance |
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COUT |
Output |
VOUT = 0V |
8 |
12 |
pF |
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Capacitance |
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NOTE: |
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2567 lnk 04 |
1. This parameter is measured at characterization but not tested.
6.21 |
3 |