Integrated Device Technology Inc IDT7207L15D, IDT7207L15J, IDT7207L15P, IDT7207L20D, IDT7207L20DB Datasheet

CMOS ASYNCHRONOUS FIFO	IDT7207
32,768 x 9

Integrated Device Technology, Inc.

FEATURES:

•32768 x 9 storage capacity

•High-speed: 15ns access time

•Low power consumption

—Active: 660mW (max.)

—Power-down: 44mW (max.)

•Asynchronous and simultaneous read and write

•Fully expandable in both word depth and width

•Pin and functionally compatible with IDT720x family

•Status Flags: Empty, Half-Full, Full

•Retransmit capability

•High-performance CMOS technology

•Military product compliant to MIL-STD-883, Class B

•Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications

DESCRIPTION:

The IDT7207 is a monolithic dual-port memory buffer with internal pointers that load and empty data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth.

Data is toggled in and out of the device through the use of the Write (W) and Read (R) pins.

The devices 9-bit width provides a bit for a control or parity at the user’s option. It also features a Retransmit (RT) capability that allows the read pointer to be reset to its initial position when RT is pulsed LOW. A Half-Full Flag is available in the single device and width expansion modes.

The IDT7207 is fabricated using IDT’s high-speed CMOS technology. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing, rate buffering, and other applications.

Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

	W	WRITE
		CONTROL

WRITE

POINTER

THREE-

STATE

BUFFERS

	READ
R	CONTROL

FLAG

LOGIC

	EXPANSION
XI	LOGIC

The IDT logo is a registered trademark of Integrated Device Techology, Inc.

DATA INPUTS (D 0 –D 8 )

RAM ARRAY

32,768 x 9 READ POINTER

RS

DATA OUTPUTS (Q 0 –Q 8 )

RESET

LOGIC

EF	FL/RT
FF

XO/HF

3140 drw 01

MILITARY AND COMMERCIAL TEMPERATURE RANGES		DECEMBER 1996
©1996 Integrated Device Technology, Inc.	For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.	DSC-3140/2

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IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9	MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

W	1		28	Vcc
D 8	2		27	D4
D 3	3		26	D5
D 2	4	P28-1	25	D6
D 1	5		24	D7
D 0	6	D28-1	23	FL/RT
XI	7		22	RS
FF	8		21	EF
Q 0	9		20	XO/HF
Q 1	10		19	Q7
Q 2	11		18	Q6
Q 3	12		17	Q5
Q 8	13		16	Q4
GND	14		15	R

3140 drw 02

DIP

TOP VIEW

INDEX	D 3		D8	W NC Vcc D 4			D 5
D2	5	4 3 2				32 31 3029		D 6
					1
D1	6						28	D 7
D0	7			J32-1			27	NC
XI	8						26	/
				&				FL RT
FF	9						25	RS
				L32-1
Q0	10						24	EF
Q1	11						23	XO HF
								/
NC	12						22	Q 7
Q2	1314		15	16 17 18 19			2021	Q 6
	Q3		Q	GND NC R Q			Q5
			8	4

3140 drw 03

PLCC/LCC

TOP VIEW

ABSOLUTE MAXIMUM RATINGS(1)

Symbol	Rating	Commercial	Military	Unit
VTERM	Terminal	–0.5 to + 7.0	–0.5 to +7.0	V
	Voltage with
	Respect to
	GND
TA	Operating	0 to +70	–55 to +125	° C
	Temperature
TBIAS	Temperature	–55 to +125	–65 to +135	° C
	Under Bias
TSTG	Storage	–55 to + 125	–65 to +155	° C
	Temperature
IOUT	DC Output	50	50	mA
	Current
NOTE:				3140 tbl 01

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING

CONDITIONS

Symbol	Parameter	Min.	Typ.	Max.		Unit
VCCM	Military Supply	4.5	5.0	5.5		V
	Voltage
VCCC	Commercial Supply	4.5	5.0	5.5		V
	Voltage
GND	Supply Voltage	0	0	0		V
VIH(1)	Input High Voltage	2.0	—	—		V
	Commercial
VIH(1)	Input High Voltage	2.2	—	—		V
	Military
VIL(1)	Input Low Voltage	—	—	0.8		V
	Commercial and
	Military
NOTE:					3140 tbl 02

1. 1.5V undershoots are allowed for 10ns once per cycle.

DC ELECTRICAL CHARACTERISTICS FOR THE 7207

(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)

				IDT7207					IDT7207
			Commercial						Military
		tA = 15, 20, 25, 35, 50 ns						tA = 20, 30, 50 ns
Symbol	Parameter	Min.		Typ.		Max.	Min.		Typ.	Max.		Unit
ILI(1)	Input Leakage Current (Any Input)	–1		—		1	–1		—	1		μA
ILO(2)	Output Leakage Current	–10		—		10	–10		—	10		μA
VOH	Output Logic “1” Voltage IOH = –2mA	2.4		—		—	2.4		—	—		V
VOL	Output Logic “0” Voltage IOL = 8mA	—		—		0.4	—		—	0.4		V
ICC1(3)	Active Power Supply Current	—		—		120(4)	—		—	150(4)		mA
ICC2(3)	Standby Current (R=W=RS=FL/RT=VIH)	—		—		12	—		—	25		mA
ICC3(L)(3)	Power Down Current (All Input = VCC - 0.2V)	—		—		8	—		—	12		mA
NOTES:											3140 tbl 04

1.Measurements with 0.4 £ VIN £ VCC.

2.R ³ VIH, 0.4 £ VOUT £ VCC.

3.ICC measurements are made with outputs open (only capacitive loading).

4.Tested at f = 20MHz.

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IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9	MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS(1)

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

		Com'l		Com'l & Mil.			Com'l		Military		Com'l	Com'l & Mil.
		7207L15		7207L20		7207L25		7207L30		7207L35		7207L50
Symbol	Parameters	Min.	Max.	Min.	Max.	Min. Max.		Min. Max.		Min.	Max.	Min. Max.			Unit
fS	Shift Frequency	—	40	—	33.3	—	28.5	—	25	—	22.2	—	15		MHz
tRC	Read Cycle Time	25	—	30	—	35	—	40	—	45	—	65	—		ns
tA	Access Time	—	15	—	20	—	25	—	30	—	35	—	50		ns
tRR	Read Recovery Time	10	—	10	—	10	—	10	—	10	—	15	—		ns
tRPW	Read Pulse Width(2)	15	—	20	—	25	—	30	—	35	—	50	—		ns
tRLZ	Read LOW to Data Bus LOW(3)	5	—	5	—	5	—	5	—	5	—	10	—		ns
tWLZ	Write HIGH to Data Bus Low-Z(3, 4)	5	—	5	—	5	—	5	—	10	—	15	—		ns
tDV	Data Valid from Read HIGH	5	—	5	—	5	—	5	—	5	—	5	—		ns
tRHZ	Read HIGH to Data Bus High-Z(3)	—	15	—	15	—	18	—	20	—	20	—	30		ns
tWC	Write Cycle Time	25	—	30	—	35	—	40	—	45	—	65	—		ns
tWPW	Write Pulse Width(2)	15	—	20	—	25	—	30	—	35	—	50	—		ns
tWR	Write Recovery Time	10	—	10	—	10	—	10	—	10	—	15	—		ns
tDS	Data Set-up Time	11	—	12	—	15	—	18	—	18	—	30	—		ns
tDH	Data Hold Time	0	—	0	—	0	—	0	—	0	—	5	—		ns
tRSC	Reset Cycle Time	25	—	30	—	35	—	40	—	45	—	65	—		ns
tRS	Reset Pulse Width(2)	15	—	20	—	25	—	30	—	35	—	50	—		ns
tRSS	Reset Set-up Time(3)	15	—	20	—	25	—	30	—	35	—	50	—		ns
tRTR	Reset Recovery Time	10	—	10	—	10	—	10	—	10	—	15	—		ns
tRTC	Retransmit Cycle Time	25	—	30	—	35	—	40	—	45	—	65	—		ns
tRT	Retransmit Pulse Width(2)	15	—	20	—	25	—	30	—	35	—	50	—		ns
tRTS	Retransmit Set-up Time(3)	15	—	20	—	25	—	30	—	35	—	50	—		ns
tRSR	Retransmit Recovery Time	10	—	10	—	10	—	10	—	10	—	15	—		ns
tEFL	Reset to EF LOW	—	25	—	30	—	35	—	40	—	45	—	65		ns
tHFH, tFFH	Reset to HF and FF HIGH	—	25	—	30	—	35	—	40	—	45	—	65		ns
tRTF	Retransmit LOW to Flags Valid	—	25	—	30	—	35	—	40	—	45	—	65		ns
tREF	Read LOW to EF LOW	—	15	—	20	—	25	—	30	—	30	—	45		ns
tRFF	Read HIGH to FF HIGH	—	15	—	20	—	25	—	30	—	30	—	45		ns
tRPE	Read Pulse Width after EF HIGH	15	—	20	—	25	—	30	—	35	—	50	—		ns
tWEF	Write HIGH to EF HIGH	—	15	—	20	—	25	—	30	—	30	—	45		ns
tWFF	Write LOW to FF LOW	—	15	—	20	—	25	—	30	—	30	—	45		ns
tWHF	Write LOW to HF Flag LOW	—	25	—	30	—	35	—	40	—	45	—	65		ns
tRHF	Read HIGH to HF Flag HIGH	—	25	—	30	—	35	—	40	—	45	—	65		ns
tWPF	Write Pulse Width after FF HIGH	15	—	20	—	25	—	30	—	35	—	50	—		ns
tXOL	Read/Write LOW to XO LOW	—	15	—	20	—	25	—	30	—	35	—	50		ns
tXOH	Read/Write HIGH to XO HIGH	—	15	—	20	—	25	—	30	—	35	—	50		ns
tXI	XI Pulse Width(2)	15	—	20	—	25	—	30	—	35	—	50	—		ns
tXIR	XI Recovery Time	10	—	10	—	10	—	10	—	10	—	10	—		ns
tXIS	XI Set-up Time	10	—	10	—	10	—	10	—	15	—	15	—		ns
NOTES:														3140 tbl 05

1.Timings referenced as in AC Test Conditions.

2.Pulse widths less than minimum are not allowed.

3.Values guaranteed by design, not currently tested.

4.Only applies to read data flow-through mode.

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IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9	MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS

Input Pulse Levels	GND to 3.0V
Input Rise/Fall Times	5ns
Input Timing Reference Levels	1.5V
Output Reference Levels	1.5V
Output Load	See Figure 1
	3140 tbl 07

CAPACITANCE(1) (TA = +25°C, f = 1.0 MHz)

	Symbol	Parameter	Condition	Max.	Unit
	CIN(1)	Input Capacitance	VIN = 0V	10	pF
	COUT(1,2)	Output Capacitance	VOUT = 0V	10	pF
	NOTES:				3140 tbl 08

1.This parameter is sampled and not 100% tested.

2.With output deselected.

SIGNAL DESCRIPTIONS

Inputs:

DATA IN (D0–D8) — Data inputs for 9-bit wide data.

Controls:

RESET (RS) — Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place.

Both the Read Enable (R) and Write Enable (W) inputs must be in the HIGH state during the window shown in Figure 2 (i.e. tRSS before the rising edge of RS) and should not change until tRSR after the rising edge of RS.

WRITE ENABLE (W) — A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set. Data set-up and hold times must be adhered-to, with respect to the rising edge of the Write Enable (W). Data is stored in the RAM array sequentially and independently of any on-going read operation.

After half of the memory is filled, and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LOW, and will remain set until the difference between the write pointer and read pointer is less-than or equal to one-half of the total memory of the device. The Half-Full Flag (HF) is reset by the rising edge of the read operation.

To prevent data overflow, the Full Flag (FF) will go LOW on the falling edge of the last write signal, which inhibits further write operations. Upon the completion of a valid read operation, the Full Flag (FF) will go HIGH after tRFF, allowing a new valid write to begin. When the FIFO is full, the internal write pointer is blocked from W, so external changes inWwill not affect the FIFO when it is full.

5V

1.1KΩ

D.U.T.

680Ω 30pF*

OR EQUIVALENT CIRCUIT	3140 drw 04

Figure 1. Output Load

*Includes jig and scope capacitances.

READ ENABLE (R) — A read cycle is initiated on the falling edge of the Read Enable (R), provided the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis, independent of any ongoing write operations. After Read Enable (R) goes HIGH, the Data Outputs (Q0 through Q8) will return to a high-impedance condition until the next Read operation. When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, allowing the “final” read cycle but inhibiting further read operations, with the data outputs remaining in a highimpedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after tWEF and a valid Read can then begin. When the FIFO is empty, the internal read pointer is blocked from R so external changes will not affect the FIFO when it is empty.

FIRST LOAD/RETRANSMIT (FL/RT) — This is a dualpurpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first device loaded (see Operating Modes). The Single Device Mode is initiated by grounding the Expansion In (XI).

The IDT7207 can be made to retransmit data when the Retransmit Enable Control (RT) input is pulsed LOW. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. The status of the Flags will change depending on the relative locations of the read and write pointers. Read Enable (R) and Write Enable (W) must be in the HIGH state during retransmit. This feature is useful when less than 32,768 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode.

EXPANSION IN (XI) — This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy-Chain Mode.

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