Integrated Device Technology Inc IDT54FCT162511ATPV, IDT54FCT162511ATPVB, IDT54FCT162511CTE, IDT54FCT162511CTEB, IDT54FCT162511CTPAB Datasheet

FAST CMOS 16-BIT	IDT54/74FCT162511AT/CT
REGISTERED/LATCHED
TRANSCEIVER WITH PARITY

Integrated Device Technology, Inc.

FEATURES:

•0.5 MICRON CMOS Technology

•Typical tsk(o) (Output Skew) < 250ps, clocked mode

•Low input and output leakage ≤1μA (max)

•ESD > 2000V per MIL-STD-883, Method 3015;

>200V using machine model (C = 200pF, R = 0)

•Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack

•Extended commercial range of –40°C to +85°C

•VCC = 5V ±10%

• Balanced Output Drivers:	±24mA	(commercial)
	±16mA	(military)

•Series current limiting resistors

•Generate/Check, Check/Check modes

•Open drain parity error allows wire-OR

DESCRIPTION:

The FCT162511AT/CT 16-bit registered/latched transceiver with parity is built using advanced dual metal CMOS technology. This high-speed, low-power transceiver combines D-

type latches and D-type flip-flops to allow data flow in transparent, latched or clocked modes. The device has a parity generator/cheker in the A-to-B direction and a parity checker in the B-to-A direction. Error checking is done at the byte level with separate parity bits for each byte. Separate error flags exits for each direction with a single error flag indicating an error for either byte in the A-to-B direction and a second error flag indicating an error for either byte in the B-to-A direction. The parity error flags are open drain outputs which can be tied together and/or tied with flags from other devices to form a single error flag or interrupt. The parity error flags are enabled by the OExx control pins allowing the designer to disable the error flag during combinational transitions.

The control pins LEAB, CLKAB and OEAB control operation in the A-to-B direction while LEBA, CLKBA and OEBA control the B-to-A direction. GEN/CHK is only for the selection of A-to-B operation, the B-to-A direction is always in checking mode. The ODD/EVEN select is common between the two directions. Except for the ODD/EVEN control, independent operation can be achieved between the two directions by using the corresponding control lines.

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM:

LEAB
CLKAB				OEAB
	Data		Parity, data	B0-15
	16
			18	PB1,2
		Parity
			Latch/
GEN/CHK
	Byte	2	Register
				PERB
	Parity
A0-15	Generator/			(Open Drain)
	Checker
PA1,2
ODD/EVEN
				LEBA
				CLKBA
	Parity, data		Parity, Data
	18		18
			Latch/
OEBA
			Register
			Byte
PERA			Parity
			Checking
(Open Drain)
				2916 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES		AUGUST 1996
©1996 Integrated Device Technology, Inc.	5.11	DSC–2916/5

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IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY	MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL BLOCK DIAGRAM

ODD/EVEN

OEAB

LEBA

CLKBA

CLKAB

	LEAB		C	C
					B0 - B7
	A0 - A7		D	D
				C
				C
				D
	OEBA			D
		P	C	C
		O			PB1
	PA1		D	D
		I		C	P
				C
				D
				D
			C	C	B8 - B15
	A8 - A15		D	D
				C
				C
				D
				D
		P	C	C
		O			PB2
	PA2		D	D
		I
				C
				C
				D
				D
			C	C
	GEN/CHK		D	D	PERB
					(Open Drain)
				C
	PERA			C
				D
	(Open Drain)			D	P
					2916 drw 02

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IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY	MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

OEAB		1		56		GEN/CHK
LEAB		2		55		CLKAB
PA1		3		54		PB1
GND		4		53		GND
A0		5		52		B0
A1		6		51		B1
VCC		7		50		VCC
A2		8		49		B2
A3		9		48		B3
A4		10		47		B4
A5		11		46		B5
A6		12		45		B6
A7		13		44		B7
GND		14	SO56-1	43		PERB
PERA		15	SO56-2	42		GND
			SO56-3
A8		16		41		B8
A9		17		40		B9
A10		18		39		B10
A11		19		38		B11
A12		20		37		B12
A13		21		36		B13
VCC		22		35		VCC
A14		23		34		B14
A15		24		33		B15
GND		25		32		GND
PA2		26		31		PB2
OEBA		27		30		CLKBA
LEBA		28		29		ODD/EVEN

OEAB		1	56		GEN/CHK
LEAB		2	55		CLKAB
PA1		3	54		PB1
GND		4	53		GND
A0		5	52		B0
A1		6	51		B1
VCC		7	50		VCC
A2		8	49		B2
A3		9	48		B3
A4		10	47		B4
A5		11	46		B5
A6		12	45		B6
A7		13	44		B7
GND		14	E56-1 43		PERB
PERA		15	42		GND
A8		16	41		B8
A9		17	40		B9
A10		18	39		B10
A11		19	38		B11
A12		20	37		B12
A13		21	36		B13
VCC		22	35		VCC
A14		23	34		B14
A15		24	33		B15
GND		25	32		GND
PA2		26	31		PB2
OEBA		27	30		CLKBA
LEBA		28	29		ODD/EVEN

SSOP/	CERPACK
TSSOP/TVSOP
TOP VIEW	TOP VIEW
2916 drw 03	2916 drw 04

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2916 lnk 01

IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY	MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)

Symbol	Description	Max.	Unit
VTERM(2)	Terminal Voltage with Respect to	–0.5 to +7.0	V
	GND
VTERM(3)	Terminal Voltage with Respect to	–0.5 to	V
	GND	VCC +0.5
TSTG	Storage Temperature	–65 to +150	°C
IOUT	DC Output Current	–60 to +120	mA

NOTES:

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.Open drain and all device terminals except FCT162XXXT Output and I/O terminals.

3.Output and I/O terminals for FCT162XXXT.

FUNCTION TABLE(1,4)

	Inputs			Outputs
OEAB	LEAB	CLKAB	Ax	Bx
H	X	X	X	Z
L	H	X	L	L
L	H	X	H	H
L	L	−	L	L
L	L	−	H	H
L	L	L	X	B(2)
L	L	H	X	B(3)
NOTES:				2916 tbl 02

1.A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.

2.Output level before the indicated steady-state input conditions were established.

3.Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.

4.H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care

Z = High Impedance

− = LOW-to-HIGH Transition

PIN DESCRIPTION

Pin Names	Description
OEAB	A-to-B Output Enable Input (Active LOW)
OEBA	B-to-A Output Enable Input (Active LOW)
LEAB	A-to-B Latch Enable Input
LEBA	B-to-A Latch Enable Input
CLKAB	A-to-B Clock Input
CLKBA	B-to-A Clock Input
Ax	A-to-B Data Inputs or B-to-A 3-State Outputs
Bx	B-to-A Data Inputs or A-to-B 3-State Outputs
PERA	Parity Error (Open Drain) on A Outputs
PERB	Parity Error (Open Drain) on B Outputs
PAx(1)	A-to-B Parity Input, B-to-A Parity Output
PBx	B-to-A Parity Input, A-to-B Parity Output
ODD/EVEN	Parity Mode Selection Input
GEN/CHK	A to B Port Generate or Check Mode Input
NOTES:	2916 tbl 03

1.The PAx pin input is internally disabled during parity generation. This means that when generating parity in the A to B direction there is no need to add a pull up resistor to guarantee state. The pin will still function properly as the parity output for the B to A direction.

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