IDT IDT54FCT16841AT, IDT54FCT16841BT, IDT54FCT16841CT, IDT54FCT16841ET, IDT54FCT162841AT User Manual
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IDT54FCT162841ATE
FAST CMOS 20-BIT |
IDT54/74FCT16841AT/BT/CT/ET |
TRANSPARENT |
IDT54/74FCT162841AT/BT/CT/ET |
LATCHES |
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Integrated Device Technology, Inc.
FEATURES:
•Common features:
–0.5 MICRON CMOS Technology
–High-speed, low-power CMOS replacement for ABT functions
–Typical tSK(o) (Output Skew) < 250ps
–Low input and output leakage ≤1μA (max.)
–ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
–Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
–Extended commercial range of -40°C to +85°C
–VCC = 5V ±10%
•Features for FCT16841AT/BT/CT/ET:
–High drive outputs (-32mA IOH, 64mA IOL)
–Power off disable outputs permit “live insertion”
–Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C
•Features for FCT162841AT/BT/CT/ET:
–Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
–Reduced system switching noise
–Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,TA = 25°C
DESCRIPTION:
The FCT16841AT/BT/CT/ET and FCT162841AT/BT/CT/ ET 20-bit transparent D-type latches are built using advanced dual metal CMOS technology. These high-speed, low-power latches are ideal for temporary storage of data. They can be used for implementing memory address latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls are organized to operate each device as two 10-bit latches or one 20-bit latch. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin.
The FCT16841AT/BT/CT/ET are ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers.
The FCT162841AT/BT/CT/ET have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times–reducing the need for external series terminating resistors. The FCT162841AT/BT/CT/ET are plug-in replacements for the FCT16841AT/BT/CT/ET and ABT16841 for on-board interface applications.
FUNCTIONAL BLOCK DIAGRAM
1OE |
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2OE |
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1LE |
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2LE |
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1D1 |
D |
2D1 |
D |
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1Q1 |
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2Q1 |
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C |
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C |
TO 9 OTHER CHANNELS TO 9 OTHER CHANNELS
2556 drw 01 |
2556 drw 02 |
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
JULY 1996 |
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©1996 Integrated Device Technology, Inc. |
5.18 |
DSC-2556/7 |
1
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET |
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FAST CMOS 20-BIT TRANSPARENT LATCHES |
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
PIN CONFIGURATIONS
1OE |
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1 |
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56 |
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1LE |
1Q1 |
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2 |
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55 |
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1D1 |
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1Q2 |
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3 |
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54 |
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1D2 |
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GND |
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4 |
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53 |
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GND |
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1Q3 |
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5 |
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52 |
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1D3 |
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1Q4 |
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6 |
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51 |
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1D4 |
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VCC |
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7 |
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50 |
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VCC |
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1Q5 |
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8 |
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49 |
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1D5 |
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1Q6 |
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9 |
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48 |
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1D6 |
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1Q7 |
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10 |
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47 |
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1D7 |
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GND |
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11 |
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46 |
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GND |
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1Q8 |
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12 |
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45 |
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1D8 |
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1Q9 |
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13 |
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44 |
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1D9 |
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1Q10 |
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14 |
SO56-1 |
43 |
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1D10 |
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15 |
SO56-2 |
42 |
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2D1 |
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2Q1 |
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SO56-3 |
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2Q2 |
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16 |
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41 |
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2D2 |
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2Q3 |
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17 |
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40 |
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2D3 |
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GND |
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18 |
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39 |
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GND |
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2Q4 |
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19 |
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38 |
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2D4 |
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2Q5 |
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20 |
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37 |
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2D5 |
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2Q6 |
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21 |
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36 |
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2D6 |
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VCC |
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22 |
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35 |
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VCC |
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2Q7 |
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23 |
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34 |
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2D7 |
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2Q8 |
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24 |
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33 |
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2D8 |
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GND |
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25 |
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32 |
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GND |
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2Q9 |
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26 |
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31 |
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2D9 |
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2Q10 |
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27 |
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30 |
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2D10 |
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2OE |
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28 |
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29 |
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2LE |
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2556 drw 03
SSOP/
TSSOP/TVSOP
TOP VIEW
1OE |
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1 |
56 |
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1LE |
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1Q1 |
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2 |
55 |
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1D1 |
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1Q2 |
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3 |
54 |
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1D2 |
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GND |
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4 |
53 |
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GND |
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1Q3 |
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5 |
52 |
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1D3 |
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1Q4 |
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6 |
51 |
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1D4 |
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VCC |
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7 |
50 |
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VCC |
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1Q5 |
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8 |
49 |
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1D5 |
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1Q6 |
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9 |
48 |
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1D6 |
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1Q7 |
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10 |
47 |
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1D7 |
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GND |
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11 |
46 |
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GND |
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1Q8 |
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12 |
45 |
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1D8 |
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1Q9 |
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13 |
44 |
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1D9 |
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1Q10 |
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14 |
E56-1 43 |
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1D10 |
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2Q1 |
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15 |
42 |
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2D1 |
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2Q2 |
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16 |
41 |
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2D2 |
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2Q3 |
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17 |
40 |
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2D3 |
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GND |
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18 |
39 |
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GND |
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2Q4 |
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19 |
38 |
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2D4 |
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2Q5 |
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20 |
37 |
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2D5 |
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2Q6 |
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21 |
36 |
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2D6 |
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VCC |
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22 |
35 |
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VCC |
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2Q7 |
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23 |
34 |
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2D7 |
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2Q8 |
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24 |
33 |
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2D8 |
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GND |
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25 |
32 |
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GND |
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2Q9 |
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26 |
31 |
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2D9 |
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2Q10 |
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27 |
30 |
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2D10 |
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2OE |
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28 |
29 |
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2LE |
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2556 drw 04
CERPACK
TOP VIEW
5.18 |
2 |
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET |
|
FAST CMOS 20-BIT TRANSPARENT LATCHES |
MILITARY AND COMMERCIAL TEMPERATURE RANGES |
PIN DESCRIPTION |
|
FUNCTION TABLE(1) |
|
|
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Pin Names |
Description |
|
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Inputs |
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Outputs |
xDx |
Data Inputs |
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xDx |
xLE |
xOE |
xQx |
xLE |
Latch Enable Input (Active HIGH) |
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H |
H |
L |
H |
xOE |
Output Enable Input (Active LOW) |
|
L |
H |
L |
L |
xQx |
3-State Outputs |
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X |
L |
L |
Q(2) |
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2556 tbl 01 |
X |
X |
H |
Z |
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NOTES: |
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2556 tbl 02 |
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1. H = HIGH Voltage Level |
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L = LOW Voltage Level |
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X = Don’t Care
Z = High Impedance
2. Output level before xLE HIGH-to-LOW Transition.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Description |
Max. |
Unit |
VTERM(2) |
Terminal Voltage with Respect to |
–0.5 to +7.0 |
V |
|
GND |
|
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VTERM(3) |
Terminal Voltage with Respect to |
–0.5 to |
V |
|
GND |
VCC +0.5 |
|
|
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TSTG |
Storage Temperature |
–65 to +150 |
°C |
IOUT |
DC Output Current |
–60 to +120 |
mA |
NOTES: |
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2556 lnk 03 |
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1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.All device terminals except FCT162XXXT Output and I/O terminals.
3.Output and I/O terminals for FCT162XXXT.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol |
Parameter(1) |
Conditions |
Typ. |
Max. |
Unit |
CIN |
Input |
VIN = 0V |
3.5 |
6.0 |
pF |
|
Capacitance |
|
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COUT |
Output |
VOUT = 0V |
3.5 |
8.0 |
pF |
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Capacitance |
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NOTE: |
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2556 lnk 04 |
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1. This parameter is measured at characterization but not tested.
5.18 |
3 |
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