Integrated Device Technology Inc IDT7130LA100C, IDT7130LA100CB, IDT7130LA100F, IDT7130LA20P, IDT7130LA20PB Datasheet

									HIGH-SPEED	IDT7130SA/LA
									1K x 8 DUAL-PORT	IDT7140SA/LA
									STATIC RAM
Integrated Device Technology, Inc.

FEATURES

•High-speed access

—Military: 25/35/55/100ns (max.) —Commercial: 25/35/55/100ns (max.) —Commercial: 20ns 7130 in PLCC and TQFP

•Low-power operation —IDT7130/IDT7140SA

Active: 550mW (typ.) Standby: 5mW (typ.)

—IDT7130/IDT7140LA Active: 550mW (typ.) Standby: 1mW (typ.)

•MASTER IDT7130 easily expands data bus width to 16-or-more-bits using SLAVE IDT7140

•On-chip port arbitration logic (IDT7130 Only)

•BUSY output flag on IDT7130; BUSY input on IDT7140

•Interrupt flags for port-to-port communication

•Fully asynchronous operation from either port

•Battery backup operation–2V data retention (LA only)

•TTL-compatible, single 5V ±10% power supply

•Military product compliant to MIL-STD-883, Class B

•Standard Military Drawing #5962-86875

•Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications

DESCRIPTION

The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port Static RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" DualPort RAM together with the IDT7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-or-more-bit memory system applications results in full-speed, error-free operation without the need for additional discrete logic.

Both devices provide two independent ports with separate control, address, and I/O pins that permit independent asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode.

Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 550mW of power. Low-power (LA) versions offer battery backup data retention capability, with each Dual-Port typically consuming 200μW from a 2V battery.

The IDT7130/IDT7140 devices are packaged in 48-pin sidebraze or plastic DIPs, LCCs, or flatpacks, 52-pin PLCC, and 64-pin TQFP and STQFP. Military grade product is manufactured in compliance with the latest revision of MIL- STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.

FUNCTIONAL BLOCK DIAGRAM

OEL	OER
CEL	CER
R/WL	R/WR

I/O0L- I/O7L			I/O				I/O			I/O0R-I/O7R
			Control			Control
(1,2)										(1,2)
BUSYL										BUSYR
A9L										A9R
	Address				MEMORY				Address
A0L	Decoder				ARRAY				Decoder	A0R

10	10

	NOTES:		ARBITRATION
	1. IDT7130 (MASTER): BUSY is open
		CEL	and	CER
	drain output and requires pullup
		OEL	INTERRUPT	OER
	resistor of 270Ω.		LOGIC
		R/WL		R/WR
	IDT7140 (SLAVE): BUSY is input.
	2. Open drain output: requires pullup
	resistor of 270Ω.
	(2)
	INTL

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

(2)

INTR

2689 drw 01

MILITARY AND COMMERCIAL TEMPERATURE RANGES		OCTOBER 1996
©1996 Integrated Device Technology, Inc. For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.		DSC-2689/7

6.01

1

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS	MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS (1,2)

CEL		1		48		VCC
R/WL		2		47		CER
BUSYL		3		46		R/ R
		4		45		W
INTL						BUSYR
OEL		5		44		INTR
A0L		6		43		OER
A1L		7		42		A0R
A2L		8	IDT7130/	41		A1R
A3L		9	IDT7140	40		A2R
A4L		10	P48-1	39		A3R
A5L		11	&	38		A4R
			C48-2
A6L		12		37		A5R
A7L		13	DIP	36		A6R
A8L		14	TOP	35		A7R
			VIEW (3)
A9L		15		34		A8R
I/O0L		16		33		A9R
I/O1L		17		32		I/O7R
I/O2L		18		31		I/O6R
I/O3L		19		30		I/O5R
I/O4L		20		29		I/O4R
I/O5L		21		28		I/O3R
I/O6L		22		27		I/O2R
I/O7L		23		26		I/O1R
GND		24		25		I/O0R

2689 drw 02

L

R

INDEX

A0L

OEL

N/C

INTL

BUSY

R/WL CEL

VCC RCE

R/WR BUSY

INTR

N/C

7

6

5

4

3

2

52 51 50 49 48 47

A1L

8

1

A2L

9

A3L

10

A4L

11

A5L

12

IDT7130/40

A6L

13

J52-1

A7L

14

52-PIN PLCC

A8L

15

TOP VIEW (3)

A9L

16

I/O0L

17

I/O1L

18

I/O2L

19

I/O3L

20

21 22 23 24 25 26 27 28 29 30 31 32 33

I/O4L

I/O5L

I/O6L

I/O7L

N/C

GND I/O0R

I/O1R I/O2R

I/O3R I/O4R

I/O5R

I/O6R

46 OER

45 A0R

44 A1R

43 A2R

42 A3R

41 A4R

40 A5R

39 A6R

38 A7R

37 A8R

36 A9R

35 N/C

34 I/O7R

2689 drw 04

L

R

INDEX

A0L

OEL

INTL

BUSY

R/WL

CEL VCC CER

R/WR

BUSY

INTR OER

6

5

4

3

2

48 47 46 45 44 43

1

A1L

7

A2L

8

A3L

9

A4L

10

IDT7130/40

A5L

11

L48-1

A6L

12

&

F48-1

A7L

13

48-PIN LCC/ FLATPACK

A8L

14

TOP VIEW (3)

A9L

15

I/O0L

16

I/O1L

17

I/O2L

18

19 20 21 22 23 24 25 26 27 28 29 30

I/O3L

I/O4L

I/O5L

I/O6L

I/O7L

GND I/O0R I/O1R

I/O2R

I/O3R

I/O4R I/O5R

NOTES:

1.All Vcc pins must be connected to the power supply.

2.All GND pins must be connected to the ground supply.

42	A0R
41	A1R
40	A2R
39	A3R
38	A4R
37	A5R
36	A6R
35	A7R
34	A8R
33	A9R
32	I/O7R
31	I/O6R

2689 drw 03

3. This text does not indicate orientation of the actual part-marking.

														L													R
INDEX					N/C		N/C		N/C INTL BUSY R/WL CEL VCC												VCC CER R/WR BUSY INTR N/C												N/C		N/C
					64		63		62		61		60		59		58		57		56		55		54		53		52		51		50		49
OEL					1																																48		OER
A0L					2																																47		A0R
A1L					3																																46		A1R
A2L					4																																45		A2R
A3L					5																																44		A3R
A4L					6												IDT7130/40																				43		A4R
A5L					7										PP64-1 & PN64-1																						42		A5R
A6L					8										64-PIN STQFP																						41		A6R
N/C					9											64-PIN TQFP																					40		N/C
A7L					10											TOP VIEW (3)																					39		A7R
A8L					11																																38		A8R
A9L					12																																37		A9R
N/C					13																																36		N/C
I/O0L					14																																35		N/C
I/O1L					15		18		19		20		21		22		23		24		25		26		27		28		29		30		31		32		34		I/O7R
I/O2L					17																																33		I/O6R
					16
																																					2689 drw 05
					I/O3L		N/C		I/O4L		I/O5L		I/O6L		I/O7L		N/C		GND		GND		I/O0R		I/O1R		I/O2R		I/O3R		N/C		I/O4R		I/O5R

6.01

2

2689 tbl 01

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS	MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)

Symbol	Rating	Commercial	Military	Unit
VTERM(2)	Terminal Voltage	–0.5 to +7.0	–0.5 to +7.0	V
	with Respect to
	GND
TA	Operating	0 to +70	–55 to +125	°C
	Temperature
TBIAS	Temperature	–55 to +125	–65 to +135	°C
	Under Bias
TSTG	Storage	–55 to +125	–65 to +150	°C
	Temperature
IOUT	DC Output	50	50	mA
	Current

RECOMMENDED

DC OPERATING CONDITIONS

Symbol	Parameter	Min.	Typ.	Max.	Unit
VCC	Supply Voltage	4.5	5.0	5.5	V
GND	Supply Voltage	0	0	0	V
VIH	Input High Voltage	2.2	—	6.0(2)	V
VIL	Input Low Voltage	–0.5(1)	—	0.8	V

NOTES:

2689 tbl 02

1.VIL (min.) > -1.5V for pulse width less than 10ns.

2.VTERM must not exceed Vcc + 0.5V.

NOTES:

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.5V.

RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE

	Ambient
Grade	Temperature	GND	VCC
Military	–55°C to +125°C	0V	5.0V ± 10%
Commercial	0°C to +70°C	0V	5.0V ± 10%

2689 tbl 03

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)

			7130SA		7130LA
			7140SA		7140LA
Symbol	Parameter	Test Conditions	Min.	Max.	Max.	Max.	Unit
|lLl|	Input Leakage	VCC = 5.5V,	—	10	—	5	μA
	Current(1)	VIN = 0V to VCC
|lLO|	Output Leakage	VCC = 5.5V,	—	10	—	5	μA
	Current(1)	CE = VIH, VOUT = 0V to VCC
VOL	Output Low Voltage	lOL = 4mA	—	0.4	—	0.4	V
	(l/O0-l/O7)
VOL	Open Drain Output	lOL = 16mA	—	0.5	—	0.5	V
	Low Voltage (BUSY, INT)
VOH	Output High Voltage	lOH = -4mA	2.4	—	2.4	—	V
NOTE:							2689 tbl 04

1. At Vcc < 2.0V leakages are undefined.

CAPACITANCE(1)

(TA = +25°C, f = 1.0MHz) TQFP ONLY(3)

Symbol	Parameter	Conditions(2)	Max.	Unit
CIN	Input Capacitance	VIN = 3dV	9	pF
COUT	Output Capacitance	VIN = 3dV	10	pF

NOTES:	2689 tbl 05

1.This parameter is determined by device characterization but is not production tested.

2.3dv references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.

3.11pF max. for other packages.

6.01

3

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS	MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,6) (VCC = 5.0V ± 10%)

					7130X20(2)		7130X25(3)		7130X35		7130X55		7130X100
							7140X25(3)		7140X35		7140X55		7140X100
Symbol	Parameter	Test Conditions	Version		Typ. Max.		Typ. Max.		Typ. Max.		Typ. Max.		Typ. Max.		Unit
ICC	Dynamic Operating	CEL and CER = VIL,	MIL.	SA	—	—	110	280	110	230	110	190	110	190	mA
	Current (Both Ports	Outputs open,		LA	—	—	110	220	110	170	110	140	110	140
	Active)	f = fMAX(4)	COM'L. SA		110	250	110	220	110	165	110	155	110	155
				LA	110	200	110	170	110	120	110	110	110	110
ISB1	Standby Current	CEL and CER = VIH,	MIL.	SA	—	—	30	80	25	80	20	65	20	65	mA
	(Both Ports - TTL	f = fMAX(4)		LA	—	—	30	60	25	60	20	45	20	45
	Level Inputs)		COM'L. SA		30	65	30	65	25	65	20	65	20	55
				LA	30	45	30	45	25	45	20	35	20	35
ISB2	Standby Current	CE"A" = VIL and	MIL.	SA	—	—	65	160	50	150	40	125	40	125	mA
	(One Port - TTL	CE"B" = VIH (7)		LA	—	—	65	125	50	115	40	90	40	90
	Level Inputs)	Active Port Outputs	COM'L. SA		65	165	65	150	50	125	40	110	40	110
		Open, f = fMAX(4)		LA	65	125	65	115	50	90	40	75	40	75
ISB3	Full Standby Current	CEL and	MIL.	SA	—	—	1.0	30	1.0	30	1.0	30	1.0	30	mA
	(Both Ports - All	CER > VCC -0.2V,		LA	—	—	0.2	10	0.2	10	0.2	10	0.2	10
	CMOS Level Inputs	VIN > VCC -0.2V or	COM'L. SA		1.0	15	1.0	15	1.0	15	1.0	15	1.0	15
		VIN < 0.2V,f = 0(5)		LA	0.2	5	0.2	5	0.2	4	0.2	4	0.2	4
ISB4	Full Standby Current	CE"A" < 0.2V and	MIL.	SA	—	—	60	155	45	145	40	110	40	110	mA
	(One Port - All	CE"B" > VCC -0.2V(7)		LA	—	—	60	115	45	105	40	85	40	80
	CMOS Level Inputs)	VIN > VCC -0.2V or	COM'L. SA		60	155	60	145	45	110	40	100	40	95
		VIN < 0.2V,		LA	60	115	60	105	45	85	40	70	40	70
		Active Port Outputs
		Open, f = fMAX(4)
NOTES:														2689 tbl 06

1.'X' in part numbers indicates power rating (SA or LA).

2.Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP packages.

3.Not available in DIP packages.

4.At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input levels of GND to 3V.

5.f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

6.Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100 mA (Typ.)

7.Port "A" may be either left or right port. Port "B" is opposite from port "A".

DATA RETENTION CHARACTERISTICS (LA Version Only)

		Test Conditions		lDT7130LA/IDT7140LA
Symbol	Parameter			Min.	Typ.(1)	Max.	Unit
VDR	VCC for Data Retention			2.0	—	—	V
ICCDR	Data Retention Current		Mil.	—	100	4000	μA
		VCC = 2.0V, CE > VCC -0.2V	Com’l.	—	100	1500	μA
tCDR(3)	Chip Deselect to Data	VIN > VCC -0.2V or VIN < 0.2V		0	—	—	ns
	Retention Time
tR(3)	Operation Recovery			tRC(2)	—	—	ns
	Time
NOTES:							2689 tbl 07

1.VCC = 2V, TA = +25°C, and is not production tested.

2.tRC = Read Cycle Time

3.This parameter is guaranteed but not production tested.

6.01

4

IDT7130SA/LA AND IDT7140SA/LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION WAVEFORM

DATA RETENTION MODE

VCC

VDR ³2.0V

4.5V

4.5V

CE

tCDR

VDR

tR

VIH

VIH

2692 drw 06

AC TEST CONDITIONS

Input Pulse Levels	GND to 3.0V
Input Rise/Fall Times	5ns
Input Timing Reference Levels	1.5V
Output Reference Levels	1.5V
Output Load	Figures 1, 2, and 3

2689 tbl 08

5V

1250Ω

DATA OUT

775Ω	30pF*

(*100pF for 55 and 100ns versions)

Figure 1. Output Test Load

5V

1250Ω

DATA OUT

775Ω

5pF*

Figure 2. Output Test Load (for tHZ, tLZ, tWZ, and tOW) * including scope and jig

5V

270Ω

BUSY or INT

30pF*

*100pF for 55 and 100ns versions

2689 drw 07

Figure 3. BUSY and INT

AC Output Test Load

6.01

5