Integrated Device Technology Inc. IDT29FCT52A, IDT29FCT52B, IDT29FCT52C, IDT29FCT53A, IDT29FCT53B User Manual

IDT29FCT52A

®

FAST CMOS

IDT29FCT52A/B/C

OCTAL REGISTERED

IDT29FCT53A/B/C

TRANSCEIVERS

Integrated Device Technology, Inc.

FEATURES:

•Equivalent to AMD’s Am2952/53 and National’s 29F52/53 in pinout/function

•IDT29FCT52A/53A equivalent to FAST™ speed

•IDT29FCT52B/53B 25% faster than FAST

•IDT29FCT52C/53C 37% faster than FAST

•IOL = 64mA (commercial) and 48mA (military)

•IIH and IIL only 5μA max.

•CMOS power levels (2.5mW typ. static)

•TTL input and output level compatible

•CMOS output level compatible

•Available in 24-pin DIP, SOIC, 28-pin LCC with JEDEC standard pinout

•Product available in Radiation Tolerant and Radiation Enhanced versions

•Military product compliant to MIL-STD-883, Class B

DESCRIPTION:

The IDT29FCT52A/B/C and IDT29FCT53A/B/C are 8-bit registered transceivers manufactured using an advanced dual metal CMOS technology. Two 8-bit back-to-back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable and 3-state output enable signals are provided for each register. Both A outputs and B outputs are guaranteed to sink 64mA.

The IDT29FCT52A/B/C is a non-inverting option of the IDT29FCT53A/B/C.

FUNCTIONAL BLOCK DIAGRAM(1)

CPA
CEA				OEB
A0	D0	CE CP Q0		B0
A1	D1		Q1	B1
A2	D2		Q2	B2
A3	D3	A	Q3	B3
A4	D4	Reg. Q4		B4
A5	D5		Q5	B5
A6	D6		Q6	B6
A7	D7		Q7	B7
	Q0		D0
	Q1		D1
	Q2		D2
	Q3	B	D3
	Q4 Reg. D4
	Q5		D5
	Q6		D6
	Q7	CE CP D7
OEA				CPB
				CEB
NOTE:				2533 drw 01

1. IDT29FCT52 function is shown.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FAST is a trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES		MAY 1992
©1992 Integrated Device Technology, Inc.	7.1	DSC-4605/3

1

IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS	MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

	B7	1		24	Vcc
	B6	2		23	A7
	B5	3	P24-1,	22	A6
	B4	4		21	A5
	B3	5	D24-1,	20	A4
			E24-1
	B2	6		19	A3
			&
	B1	7		18	A2
			SO24-2
	B0	8		17	A1
	OEB	9		16	A0
	CPA	10		15	OEA
	CEA	11		14	CPB
	GND	12		13	CEB

DIP/CERPACK/SOIC

TOP VIEW

INDEX

B4

B3

B2

NC

B1

B0

OEB

B5	B6	B7 NC Vcc			A7	A6
4	3	2		28 27 26
5						25	A5
			1
							A4
6						24
7						23	A3
8		L28-1				22	NC
9						21	A2
10						20	A1
11						19	A0
12 13 14 15 16 17 18
CPA	CEA	GND	NC CEB		CPB	OEA

LCC

TOP VIEW

2533 drw 02

PIN DESCRIPTION

Name	I/O	Description
A0-7	I/O	Eight bidirectional lines carrying the A Register inputs or B Register outputs.
B0-7	I/O	Eight bidirectional lines carrying the B Register inputs or A Register outputs.
CPA	I	Clock for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition
		of the CPA signal.
CEA	I	Clock Enable for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH
		transition of the CPA signal. When CEA is HIGH, the A Register holds its contents, regardless of CPA signal
		transitions.
OEB	I	Output Enable for the A Register. When OEB is LOW, the A Register outputs are enabled onto the B0-7 lines. When
		OEB is HIGH, the B0-7 outputs are in the high-impedance state.
CPB	I	Clock for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition
		of the CPB signal.
CEB	I	Clock Enable for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH
		transition of the CPB signal. When CEB is HIGH, the B Register holds its contents, regardless of CPB signal
		transitions.
OEA	I	Output Enable for the B Register. When OEA is LOW, the B Register outputs are enabled onto the A0-7 lines. When
		OEA is HIGH, the A0-7 outputs are in the high-impedance state.
		2533 tbl 01

REGISTER FUNCTION TABLE(1)

(Applies to A or B Register)

	Inputs		Internal
D	CP	CE	Q	Function
X	X	H	NC	Hold Data
L	−	L	L	Load Data
H	−	L	H
				2533 tbl 02

OUTPUT CONTROL(1)

	Internal		Y-Outputs
OE	Q	52		53	Function
H	X	Z		Z	Disable Outputs
L	L	L		H	Enable Outputs
L	H	H		L
NOTE:					2533 tbl 03

1.H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care

NC = No Change

− = LOW-to-HIGH Transition

7.1

2

IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS	MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)

Symbol	Rating	Commercial	Military	Unit
VTERM(2)	Terminal Voltage	–0.5 to +7.0	–0.5 to +7.0	V
	with Respect
	to GND
VTERM(3)	Terminal Voltage	–0.5 to VCC	–0.5 to VCC	V
	with Respect
	to GND
TA	Operating	0 to +70	–55 to +125	°C
	Temperature
TBIAS	Temperature	–55 to +125	–65 to +135	°C
	Under Bias
TSTG	Storage	–55 to +125	–65 to +150	°C
	Temperature
PT	Power Dissipation	0.5	0.5	W
IOUT	DC Output Current	120	120	mA
NOTES:			2533 tbl 04

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed +0.5V unless otherwise noted.

2.Inputs and VCC terminals only.

3.Outputs and I/O terminals only.

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol	Parameter(1)	Conditions	Typ.	Max.	Unit
CIN	Input	VIN = 0V	6	10	pF
	Capacitance
CI/O	I/O	VOUT = 0V	8	12	pF
	Capacitance
NOTE:					2533 tbl 05

1. This parameter is guaranteed by characterization data and not tested.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V

Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol

Parameter

Test Conditions(1)

Min.

Typ.(2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

—

—

V

VIL

Input LOW Level

Guaranteed Logic LOW Level

—

—

0.8

V

IIH

Input HIGH Current

VCC = Max.

VI =VCC

—

—

5

μA

(Except I/O Pins)

VI

= 2.7V

—

—

5(4)

IIL

Input LOW Current

VI

= 0.5V

—

—

–5(4)

(Except I/O Pins)

VI

= GND

—

—

–5

IIH

Input HIGH Current

VCC = Max.

VI = VCC

—

—

15

μA

(I/O Pins Only)

VI

= 2.7V

—

—

15(4)

IIL

Input LOW Current

VI

= 0.5V

—

—

–15(4)

(I/O Pins Only)

VI

= GND

—

—

–15

VIK

Clamp Diode Voltage

Vcc = Min., IN = –18mA

—

–0.7

–1.2

V

IOS

Short Circuit Current

Vcc = Max.(3), VO = GND

–60

–120

—

mA

VOH

Output HIGH Voltage

Vcc = 3V, VIN = VLC or VHC, IOH = –32μA

VHC

VCC

—

V

Vcc = Min.

IOH = –300μA

VHC

VCC

—

VIN = VIH or VIL

IOH = –15mA MIL.

2.4

4.0

—

IOH = –24mA COM’L.

2.4

4.0

—

VOL

Output LOW Voltage

Vcc = 3V, VIN = VLC or VHC, IOL = 300μA

—

GND

VLC

V

Vcc = Min.

IOL = 300μA

—

GND

VLC(4)

VIN = VIH or VIL

IOL = 48mA MIL.(5)

—

0.3

0.55

IOL = 64mA COM’L.(5)

—

0.3

0.55

NOTES:

2533 tbl 06

1.For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2.Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.

3.Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4.This parameter is guaranteed but not tested.

5.These are maximum IOL values per output, for 8 outputs turned on simultaneously. Total maximum IOL (all outputs) is 512mA for commercial and 384mA for military. Derate IOL for number of outputs exceeding 8 turned on simultaneously.

7.1

3