Integrated Device Technology Inc IDT70V24L20GI, IDT70V24L20J, IDT70V24L20JI, IDT70V24L20PF, IDT70V24L20PFI Datasheet

						HIGH-SPEED 3.3V	IDT70V24S/L
						4K x 16 DUAL-PORT
						STATIC RAM

Features

True Dual-Ported memory cells which allow simultaneous reads of the same memory location

High-speed access

–Commercial: 15/20/25/35/55ns (max.)

–Industrial: 20/25/35/55ns (max.)

Low-power operation

–IDT70V24S

Active: 400mW (typ.) Standby: 3.3mW (typ.)

–IDT70V24L

Active: 380mW (typ.) Standby: 660 W (typ.)

Separate upper-byte and lower-byte control for multiplexed bus compatibility

IDT70V24 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device

M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave

BUSY and Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling between ports

Fully asynchronous operation from either port

LVTTL-compatible, single 3.3V (±0.3V) power supply

Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP

Industrial temperature range (-40°C to +85°C) is available for selected speeds

Functional Block Diagram
R/WL				R/WR
UBL				UBR
LBL				LBR
CEL				CER
OEL				OER
I/O8L-I/O15L	I/O		I/O	I/O8R-I/O15R
I/O0L-I/O7L	Control		Control	I/O0R-I/O7R
BUSY(1,2)				BUSYR(1,2)
L
A11L	Address	MEMORY	Address	A11R
A0L	Decoder	ARRAY	Decoder	A0R
	12		12
		ARBITRATION
	CEL	INTERRUPT	CER
	OEL	SEMAPHORE	OER
		LOGIC
	R/WL		R/WR

SEML								SEMR
INTL(2)				M/S				INTR(2)
								2911 drw 01

NOTES:

1.(MASTER): BUSY is output; (SLAVE): BUSY is input.

2.BUSY outputs and INT outputs are non-tri-stated push-pull.

MARCH 2000

1

©2000IntegratedDeviceTechnology,Inc.

DSC-2911/8

IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

Description

TheIDT70V24isahigh-speed4Kx16Dual-PortStaticRAM.The IDT70V24isdesignedtobeusedasastand-alone64K-bitDual-PortRAM orasacombinationMASTER/SLAVEDual-PortRAMfor32-bit-or-more wordsystems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproach in32-bitorwidermemorysystemapplicationsresultsinfull-speed,error- free operation without the need for additional discrete logic.

Thisdeviceprovidestwoindependentportswithseparatecontrol, address,andI/Opinsthatpermitindependent,asyn-chronousaccessfor

reads or writes to any location in memory. An automatic power down featurecontrolledby CE permitstheon-chipcircuitryofeachporttoenter a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 400mW of power.

The IDT70V24 is packaged in a ceramic 84-pin PGA, an 84-Pin PLCC and a 100-pin Thin Quad Flatpack.

Pin Configurations(1,2,3)

INDEX

I/O7L

I/O6L

I/O5L

I/O4L

I/O3L

I/O2L

GND

I/O1L

I/O0L

OEL

VCC

WR/L

SEML

CEL

UBL

LBL

N/C

A11L

A10L

A9L

A8L

I/O8L		11 10						9			8			7			6			5			4			3			2			1 84 83 82 81 80 79 78 77 76 75
		12																																						74																											A7L
I/O9L		13																																						73																											A6L
I/O10L																																																																			5L
I/O11L		14																																						72																											A
		15																																						71																											A4L
I/O12L																																								70																											3L
I/O13L		16																																																																	A
		17																																						69																											A2L
GND		18																																						68																											A1L
I/O		19																																						67																											A0L
14L
I/O15L		20																										IDT70V24J												66																											INTL
VCC		21																											J84-1(4)											65																											BUSYL
GND		22																									84-Pin PLCC													64																											GND
I/O0R		23																																						63																											M/S
																											Top View(5)
1R																																																																			BUSY
I/O		24																																						62																											R
I/O2R		25																																						61																											INTR
VCC		26																																						60																											A0R
I/O		27																																						59																											A1R
3R
I/O4R		28																																						58																											A2R
I/O5R																																								57																											3R
I/O6R		29																																																																	A
																																								56																											4R
I/O		30																																																																	A
		31																																						55																											A5R
7R
I/O8R		32																																						54																											A6R
		33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

I/O9R

I/O10R

I/O11R

I/O12R

I/O13R

I/O14R

GND I/O15R

OER

WR/R

GND SEMR

CER

UBR

LBR

N/C A11R

A10R

A9R

NOTES:

1.All VCC pins must be connected to power supply.

2.All GND pins must be connected to ground supply.

3.J84-1 package body is approximately 1.15 in x 1.15 in x .17 in. PN100-1 package body is approximately 14mm x 14mm x 1.4mm.

4.This package code is used to reference the package diagram.

5.This text does not indicate orientation of the actual part-marking.

A8R	A7R	2911 drw 02
		Index		I/O9L			I/O8L I/O7L I/O6L I/O5L I/O4L											I/O3L I/O2L					GND			I/O1L			I/O0L			OEL VCC					WR/L			SEML			CEL			UBL LBL					N/C A11L					A10L
																																																											A9L			A8L			A7L			A6L
		N/C		100 99 98 97 96 95														94 93 92								91 90						89 88					87 86						85 84 83 82 81													80 79						78 77 76										N/C
				1																																																																75
		N/C		2																																																																74				N/C
		N/C		3																																																																73				N/C
		N/C		4																																																																72				N/C
		I/O10L		5																																																																71				A5L
		I/O11L		6																																																																70				A4L
		I/O12L		7																																																																69				A3L
		I/O13L		8																																																																68				A2L
		GND		9																																																																67				A1L
		I/O14L		10																									IDT70V24PF																																							66				A0L
		I/O15L		11																																																																65				INTL
																													PN100-1(4)
		VCC		12																																																																64				BUSYL
		GND		13																								100-Pin TQFP																																								63				GND
		I/O0R		14																																																																62				M/S
																													Top View(5)
		I/O1R																																																																						BUSYR
				15																																																																61
		I/O2R		16																																																																60				INTR
		VCC		17																																																																59				A0R
		I/O3R		18																																																																58				A1R
		I/O4R		19																																																																57				A2R
		I/O5R		20																																																																56				A3R
		I/O6R		21																																																																55				A4R
		N/C		22																																																																54				N/C
		N/C		23																																																																53				N/C
		N/C		24																																																																52				N/C
		N/C		25			27 28 29 30 31 32 33																34 35						36 37 38 39											40 41						42 43					44 45 46								47 48									51				N/C
				26																																																													49 50
																																																																							2911 drw 03
				I/O7R			I/O8R I/O9R I/O10R I/O11R I/O12R											I/O13R I/O14R					GND			I/O15R			OER			WR/R GND					SEMR			CER			UBR			LBR N/C					A11R A10R					A9R			A8R			A7R			A6R			A5R

6.242

	IDT70V24S/L
	High-Speed 4K x 16 Dual-Port Static RAM										Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
		63	61	60	58	55		54	51	48		46	45	42
11		I/O7L	I/O5L	I/O4L	I/O2L	I/O0L		OEL	SEML	LBL		A11L	A10L	A7L
		66	64	62	59	56		49	50	47		44	43	40
10		I/O10L	I/O8L	I/O6L	I/O3L	I/O1L		UBL	CEL	N/C		A9L	A8L	A5L
		67	65			57		53	52				41	39
09		I/O11L	I/O9L			GND		VCC	R/WL				A6L	A4L
		69	68										38	37
08		I/O13L	I/O12L										A3L	A2L
		72	71	73								33	35	34
07		I/O15L	I/O14L	VCC								BUSYL	A0L	NT
							IDT70V24G							I	L
		75	70	74				G84-3(4)				32	31	36
06		I/O0R	GND	GND			84-Pin PGA					GND	M/S	A1L
							Top View(5)
		76	77	78								28	29	30
05		I/O1R	I/O2R	VCC								A0R	INTR	BUSYR
		79	80										26	27
04		I/O3R	I/O4R										A2R	A1R
		81	83			7		11	12				23	25
03		I/O5R	I/O7R			GND		GND	SEMR				A5R	A3R
		82	1	2	5	8		10	14	17		20	22	24
02		I/O6R	I/O9R	I/O10R	I/O13R	I/O15R		R/WR	UBR	A11R		A8R	A6R	A4R
		84	3	4	6	9		15	13	16		18	19	21
01		I/O8R	I/O11R	I/O12R	I/O14R	OER		LBR	CER	N/C		A10R	A9R	A7R
		A	B	C	D	E		F	G	H		J	K		L
	Index													2911 drw 04

NOTES:

1.All VCC pins must be connected to power supply.

2.All GND pins must be connected to ground supply.

3.Package body is approximately 1.12 in x 1.12 in x .16 in.

4.This package code is used to reference the package diagram.

5.This text does not indicate orientation of the actual part-marking.

Pin Names

Left Port		Right Port	Names
CEL		CER	Chip Enable
R/WL		R/WR	Read/Write Enable
OEL		OER	Output Enable
A0L - A11L		A0R - A11R	Address
I/O0L - I/O15L		I/O0R - I/O15R	Data Input/Output
SEML		SEMR	Semaphore Enable
UBL		UBR	Upper Byte Select
LBL		LBR	Lower Byte Select
INTL		INTR	Interrupt Flag
BUSYL		BUSYR	Busy Flag
	M/S		Master or Slave Select
	VCC		Power
	GND		Ground

2911 tbl 01

6.342

IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

Truth Table I: Non-Contention Read/Write Control

					Inputs(1)				Outputs
CE		R/W		OE		UB	LB	SEM	I/O8-15	I/O0-7	Mode
H		X		X		X	X	H	High-Z	High-Z	Deselected: Power Down
X		X		X		H	H	H	High-Z	High-Z	Both Bytes Deselected
L		L		X		L	H	H	DATAIN	High-Z	Write to Upper Byte Only
L		L		X		H	L	H	High-Z	DATAIN	Write to Lower Byte Only
L		L		X		L	L	H	DATAIN	DATAIN	Write to Both Bytes
L		H		L		L	H	H	DATAOUT	High-Z	Read Upper Byte Only
L		H		L		H	L	H	High-Z	DATAOUT	Read Lower Byte Only
L		H		L		L	L	H	DATAOUT	DATAOUT	Read Both Bytes
X		X		H		X	X	X	High-Z	High-Z	Outputs Disabled
NOTE:											2911 tbl 02
1. A0L — A11L ≠		A0R — A11R

Truth Table II: Semaphore Read/Write Control(1)

			Inputs				Outputs
CE	R/W	OE		UB	LB	SEM	I/O8-15	I/O0-7	Mode
H	H	L		X	X	L	DATAOUT	DATAOUT	Read Data in Semaphore Flag
X	H	L		H	H	L	DATAOUT	DATAOUT	Read Data in Semaphore Flag
H	↑	X		X	X	L	DATAIN	DATAIN	Write DIN0 into Semaphore Flag
X	↑	X		H	H	L	DATAIN	DATAIN	Write DIN0 into Semaphore Flag
L	X	X		L	X	L	____	____	Not Allowed
L	X	X		X	L	L	____	____	Not Allowed

2911 tbl 03

NOTE:

1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.

6.442

IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

Absolute Maximum Ratings(1)

Symbol	Rating	Commercial	Unit
		& Industrial
VTERM(2)	Terminal Voltage	-0.5 to +4.6	V
	with Respect
	to GND
TBIAS	Temperature	-55 to +125	oC
	Under Bias
TSTG	Storage	-55 to +125	oC
	Temperature
IOUT	DC Output	50	mA
	Current
NOTES:			2911 tbl 04

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.VTERM must not exceed Vcc +0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period over VTERM > Vcc + 0.3V.

Capacitance

(TA = +25°C, f = 1.0MHz)

Symbol	Parameter	Conditions(2)	Max.	Unit
CIN	Input Capacitance	VIN = 3dV	9	pF
COUT	Output Capacitance	VOUT = 3dV	11	pF

2911 tbl 07

NOTES:

1.This parameter is determined by device characterization but is not production tested.

2.3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.

Maximum Operating Temperature and Supply Voltage(1)

Grade	Ambient	GND	Vcc
	Temperature
Commercial	0OC to +70OC	0V	3.3V + 0.3V
Industrial	-40OC to +85OC	0V	3.3V + 0.3V

2911 tbl 05

NOTES:

1. This is the parameter TA.

Recommended DC Operating

Conditions

Symbol	Parameter	Min.	Typ.	Max.	Unit
VCC	Supply Voltage	3.0	3.3	3.6	V
GND	Ground	0	0	0	V
VIH	Input High Voltage	2.0	____	VCC+0.3(2)	V
VIL	Input Low Voltage	-0.3(1)	____	0.8	V

2911 tbl 06

NOTES:

1.VIL> -1.5V for pulse width less than 10ns.

2.VTERM must not exceed Vcc + 0.3V.

DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)

			70V24S			70V24L
Symbol	Parameter	Test Conditions	Min.	Max.	Min.		Max.	Unit
|ILI|	Input Leakage Current(1)	VCC = 3.6V, VIN = 0V to VCC	___	10	___		5	µA
|ILO|	Output Leakage Current	CE = VIH, VOUT = 0V to VCC	___	10	___		5	µA
VOL	Output Low Voltage	IOL = +4mA	___	0.4	___		0.4	V
VOH	Output High Voltage	IOH = -4mA	2.4	___	2.4		___	V

2911 tbl 08

NOTE:

1. At VCC < 2.0V input leakages are undefined.

6.542

IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VCC = 3.3V ± 0.3V)

																70V24X15		70V24X20			70V24X25
																Com'l Only		Com'l			Com'l
																		& Ind			& Ind
Symbol	Parameter								Test Condition				Version			Typ.(2)	Max.	Typ.(2)		Max.	Typ.(2)		Max.		Unit
CC	Dynamic Operating	CE	= VIL, Outputs Open										COM'L	S	150		215	140		200	130		190		mA
I
	Current	SEM = VIH												L	140		185	130		175	125		165
	(Both Ports Active)	f = fMAX(3)
													IND	S	____		____	140		225	130		210
														L	____		____	130		195	125		180
SB1	Standby Current	CE				CE		= VIH					COM'L	S	25		35	20		30	16		30		mA
I		R and					L
	(Both Ports - TTL	SEMR = SEML = VIH												L	20		30	15		25	13		25
	Level Inputs)	f = fMAX(3)
													MIL &	S	____		____	20		45	16		45
													IND	L	____		____	15		40	13		40
SB2	Standby Current	CE		= VIL and					CE			(5)	COM'L	S	85		120	80		110	75		110		mA
I		"A"								"B" = VIH
	(One Port - TTL	Active Port Outputs Open,												L	80		110	75		100	72		95
	Level Inputs)	f=fMAX(3)
					SEM								MIL &	S	____		____	80		130	75		125
		SEM		=				L = VIH
			R										IND	L	____		____	75		115	72		110
ISB3	Full Standby Current	Both Ports CEL and											COM'L	S	1.0		5	1.0		5	1.0		5		mA
	(Both Ports -	CER > VCC - 0.2V,												L	0.2		2.5	0.2		2.5	0.2		2.5
	CMOS Level Inputs)	VIN > VCC - 0.2V or
		VIN < 0.2V, f = 0(4)											MIL &	S	____		____	1.0		15	1.0		15
		SEMR = SEML > VCC-0.2V											IND	L	____		____	0.2		5	0.2		5
SB4	Full Standby Current	CE		< 0.2V and									COM'L	S	85		125	80		115	75		105		mA
I		"A"
	(One Port -	CE"B" > VCC - 0.2V(5)												L	80		105	75		100	70		90
	CMOS Level Inputs)	SEMR = SEML > VCC-0.2V
													MIL &	S	____		____	80		130	75		120
		VIN > VCC - 0.2V or VIN < 0.2V
		Active Port Outputs Open,											IND	L	____		____	75		115	70		105
		f =	fMAX(3)
																								2911 tbl 09a
																		70V24X35			70V24X55
																		Com'l			Com'l
																		& Ind			& Ind
Symbol	Parameter										Test Condition					Version		Typ.(2)		Max.	Typ.(2)		Max.		Unit
ICC	Dynamic Operating	CE = VIL, Outputs Open														COM'L	S	120		180	120		180		mA
	Current	SEM = VIH															L	115		155	115		155
	(Both Ports Active)	f = fMAX(3)
																IND	S	120		200	120		200
																	L	115		170	115		170
ISB1	Standby Current	CER and CEL = VIH														COM'L	S	13		25	13		25		mA
	(Both Ports - TTL	SEMR = SEML = VIH															L	11		20	11		20
	Level Inputs)	f = fMAX(3)
																MIL &	S	13		40	13		40
																IND	L	11		35	11		35
ISB2	Standby Current	CE"A" = VIL and CE"B" = VIH(5)														COM'L	S	70		100	70		100		mA
	(One Port - TTL	Active Port Outputs Open,															L	65		90	65		90
	Level Inputs)	f=fMAX(3)
					SEM											MIL &	S	70		120	70		120
		SEM		=
			R					L = VIH								IND	L	65		105	65		105
ISB3	Full Standby Current	Both Ports CEL and														COM'L	S	1.0		5	1.0		5		mA
	(Both Ports -	CER > VCC - 0.2V,															L	0.2		2.5	0.2		2.5
	CMOS Level Inputs)	VIN > VCC - 0.2V or
		VIN < 0.2V, f = 0(4)														MIL &	S	1.0		15	1.0		15
		SEMR = SEML > VCC-0.2V														IND	L	0.2		5	0.2		5
ISB4	Full Standby Current	CE"A" < 0.2V and														COM'L	S	65		100	65		100		mA
	(One Port -	CE"B" > VCC - 0.2V(5)															L	60		85	60		85
	CMOS Level Inputs)	SEMR = SEML > VCC-0.2V
																MIL &	S	65		115	65		115
		VIN > VCC - 0.2V or VIN < 0.2V
		Active Port Outputs Open,														IND	L	60		100	60		100
		f =	fMAX(3)

2911 tbl 09b

NOTES:

1.'X' in part number indicates power rating (S or L)

2.VCC = 3.3V, TA = +25°C, and are not production tested. ICC DC = 115mA (typ.)

3.At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.

4.f = 0 means no address or control lines change.

5.Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6.642

IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM	Industrial and Commercial Temperature Ranges

AC Test Conditions			3.3V		3.3V
Input Pulse Levels	GND to 3.0V
Input Rise/Fall Times	3ns Max.		590Ω		590Ω
Input Timing Reference Levels	1.5V	DATAOUT		DATAOUT
Output Reference Levels	1.5V	BUSY
		INT		435Ω
Output Load	Figures 1 and 2	435Ω	30pF		5pF*
	2911 tbl 10
					2911 drw 05

Figure 1. AC Output Test Load

(for tLZ, tHZ, tWZ, tOW)

Timing of Power-Up Power-Down

CE

ICC

tPU

tPD

50%

50%

ISB

2911 drw 06 ,

Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW)

* Including scope and jig.

6.742