© 1999 Fairchild Semiconductor Corporation DS009893 www.fairchildsemi.com
July 1988
Revised November 1999
74AC299 • 74ACT299 8-Input Universal Shift/Storage Register
74AC299 • 74ACT299
8-Input Universal Shift/Storage Register
with Common Parallel I/O Pins
General Description
The AC/ACT299 is a n 8-bit universa l shift/storag e register
with 3-STATE outputs. Four modes of operation a re possi-
ble: hold (store), shift left, shift right and load data. The par-
allel load inputs and flip-flop outputs are multiplexed to
reduce the total num ber of package pins. Additiona l out-
puts are provided for flip-flops Q
0
, Q
7
to allow easy serial
cascading. A separate active LOW Master Reset is used to
reset the register.
Features
■ I
CC
and I
OZ
reduced by 5 0%
■ Common parallel I/O for reduced pin count
■ Additional serial inputs and outputs for expansion
■ Four operating modes: shift left, shift right, load
and store
■ 3-STATE outputs for bus-oriented applications
■ Outputs source/sink 24 mA
■ ACT299 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending su ffix le tter “X” to the ordering code.
Connection Diagram Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC299SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74AC299SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC299MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC299PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT299SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACT299MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT299PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
CP Clock Pulse Input
DS
0
Serial Data Input for Right Shift
DS
7
Serial Data Input for Left Shift
S
0
, S
1
Mode Select Inputs
MR
Asynchronous Master Reset
OE
1
, OE
2
3-STATE Output Enable Inputs
I/O
0
–I/O
7
Parallel Data Inputs or
3-STATE Parallel Outputs
Q
0
, Q
7
Serial Outputs