Analog Devices DAC8413FP, DAC8413EP, DAC8413BTC, DAC8412FPC, DAC8412FP Datasheet

a		Quad, 12-Bit DAC
		Voltage Output with Readback
		DAC8412/DAC8413

FEATURES

+5 V to 15 V Operation

Unipolar or Bipolar Operation True Voltage Output Double-Buffered Inputs

Reset to Min (DAC8413) or Center Scale (DAC8412) Fast Bus Access Time

Readback

APPLICATIONS

Automatic Test Equipment

Digitally Controlled Calibration

Servo Controls

Process Control Equipment

GENERAL DESCRIPTION

The DAC8412 and DAC8413 are quad, 12-bit voltage output DACs with readback capability. Built using a complementary BiCMOS process, these monolithic DACs offer the user very high package density.

Output voltage swing is set by the two reference inputs VREFH

and VREFL. By setting the VREFL input to 0 V and VREFH to a positive voltage, the DAC will provide a unipolar positive output

range. A similar configuration with VREFH at 0 V and VREFL at a negative voltage will provide a unipolar negative output range.

Bipolar outputs are configured by connecting both VREFH and VREFL to nonzero voltages. This method of setting output voltage range has advantages over other bipolar offsetting methods because it is not dependent on internal and external resistors with different temperature coefficients.

FUNCTIONAL BLOCK DIAGRAM

VLOGIC

VDD VREFH

DATA 12	I/O	INPUT
I/O	PORT	REG A
DGND		INPUT
A0		REG B
A1	CONTROL	INPUT
R/W	LOGIC	REG C
CS		INPUT
		REG D
RESET
LDAC

OUTPUT	DAC A	VOUTA
REG A
OUTPUT	DAC B	VOUTB
REG B
OUTPUT	DAC C	VOUTC
REG C
OUTPUT	DAC D	VOUTD
REG D
	VREFL	VSS

Digital controls allow the user to load or read back data from any DAC, load any DAC and transfer data to all DACs at one time.

An active low RESET loads all DAC output registers to midscale for the DAC8412 and zero scale for the DAC8413.

The DAC8412/DAC8413 are available in 28-lead plastic DIP, PLCC and LCC packages. They can be operated from a wide variety of supply and reference voltages with supplies ranging from single +5 V to ±15 V, and references from +2.5 V to ±10 V. Power dissipation is less than 330 mW with ±15 V supplies and only 60 mW with a +5 V supply.

For MIL-STD-883 applications, contact your local ADI sales office for the DAC8412/DAC8413/883 data sheet which specifies operation over the –55°C to +125°C temperature range. All 883 parts are also available on Standard Military Drawings 5962-91 76401MXA through 76404M3A.

		0.500
		0.375	+125 C
	– LSB	0.250	+25 C
		0.125
	ERROR
		0
	LINEARITY	–0.125	–55 C
		–0.250	VDD = +15V
			VSS = –15V
			VREFH = +10V
		–0.375	VREFL = –10V
			TA = –55 C, +25 C, +125 C

–0.500

0	512	1024	1536	2046	2548	2560	3072	4096
		DIGITAL INPUT CODE – Decimal

Figure 1. INL vs. Code Over Temperature

REV. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Tel: [phone]	World Wide Web Site: http://www.analog.com
Fax: [phone]	© Analog Devices, Inc., 2000

DAC8412/DAC8413–SPECIFICATIONS

	(@ VDD = +15.0 V, VSS = –15.0 V, VLOGIC = +5.0 V, VREFH = +10.0 V, VREFL = –10.0 V,
ELECTRICAL CHARACTERISTICS –40 C ≤ TA ≤ +85 C unless otherwise noted. See Note 1 for supply variations.)
Parameter	Symbol	Conditions	Min	Typ	Max	Units
Integral Nonlinearity Error	INL	E Grade		0.25	±0.5	LSB
	INL	F Grade			±1	LSB
Differential Nonlinearity Error	DNL	Monotonic Over Temperature	–1			LSB
Min-Scale Error	VZSE	RL = 2 kΩ			±2	LSB
Full-Scale Error	VFSE	RL = 2 kΩ			±2	LSB
Min-Scale Tempco	TCVZSE	RL = 2 kΩ		15		ppm/°C
Full-Scale Tempco	TCVFSE	RL = 2 kΩ		20		ppm/°C
Linearity Matching		Adjacent DAC Matching		±1		LSB
REFERENCE
Positive Reference Input Voltage Range		Note 2	VREFL + 2.5		VDD – 2.5	V
Negative Reference Input Voltage Range		Note 2	–10		VREFH – 2.5	V
Reference High Input Current	IREFH		–2.75	+1.5	+2.75	mA
Reference Low Input Current	IREFL		0	+2	+2.75	mA
Large Signal Bandwidth	BW	–3 dB, VREFH = 0 V to +10 V p-p		160		kHz
AMPLIFIER CHARACTERISTICS		RL = 2 kΩ, CL = 100 pF
Output Current	IOUT		–5		+5	mA
Settling Time	tS	to 0.01%, 10 V Step, RL = 1 kΩ		10		µs
Slew Rate	SR	10% to 90%		2.2		V/µs
Analog Crosstalk				72		dB
LOGIC CHARACTERISTICS		TA = +25°C
Logic Input High Voltage	VINH		2.4			V
Logic Input Low Voltage	VINL	TA = +25°C			0.8	V
Logic Output High Voltage	VOH	IOH = +0.4 mA	2.4			V
Logic Output Low Voltage	VOL	IOL = –1.6 mA			0.4	V
Logic Input Current	IIN				1	µA
Input Capacitance	CIN			8		pF
Digital Feedthrough3		VREFH = +2.5 V, VREFL = 0 V		5		nV-s
LOGIC TIMING CHARACTERISTICS3		Note 4
Chip Select Write Pulsewidth	tWCS		80			ns
Write Setup	tWS	tWCS = 80 ns	0			ns
Write Hold	tWH	tWCS = 80 ns	0			ns
Address Setup	tAS		0			ns
Address Hold	tAH		0			ns
Load Setup	tLS		70			ns
Load Hold	tLH		30			ns
Write Data Setup	tWDS	tWCS = 80 ns	20			ns
Write Data Hold	tWDH	tWCS = 80 ns	0			ns
Load Data Pulsewidth	tLDW		170			ns
Reset Pulsewidth	tRESET		140			ns
Chip Select Read Pulsewidth	tRCS		130			ns
Read Data Hold	tRDH	tRCS = 130 ns	0			ns
Read Data Setup	tRDS	tRCS = 130 ns	0			ns
Data to Hi Z	tDZ	CL = 10 pF			200	ns
Chip Select to Data	tCSD	CL = 100 pF			160	ns
SUPPLY CHARACTERISTICS		14.25 V ≤ VDD ≤ 15.75 V
Power Supply Sensitivity	PSS				150	ppm/V
Positive Supply Current	IDD	VREFH = +2.5 V		8.5	12	mA
Negative Supply Current	ISS		–10	–6.5		mA
Power Dissipation	PDISS				330	mW

NOTES

1All supplies can be varied ± 5%, and operation is guaranteed. Device is tested with nominal supplies. 2Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 3All parameters are guaranteed by design.

4All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

Specifications subject to change without notice.

–2–

REV. D

DAC8412/DAC8413

	(@ VDD = VLOGIC = +5.0 V 5%, VSS = 0.0 V, VREFH = +2.5 V, VREFL = 0.0 V, and VSS = –5.0 V 5%,
ELECTRICAL CHARACTERISTICS VREFL = –2.5 V, –40 C ≤ TA ≤ +85 C unless otherwise noted. See Note 1 for supply variations.)
Parameter	Symbol	Conditions	Min	Typ	Max	Units
Integral Nonlinearity Error	INL	E Grade		1/2	±1	LSB
	INL	F Grade			±2	LSB
	INL	VSS = 0.0 V; E Grade2			±2	LSB
	INL	VSS = 0.0 V; F Grade2			±4	LSB
Differential Nonlinearity Error	DNL	Monotonic Over Temperature	–1		±4	LSB
Min-Scale Error	VZSE	VSS = –5.0 V				LSB
Full-Scale Error	VFSE	VSS = –5.0 V			±4	LSB
Min-Scale Error	VZSE	VSS = 0.0 V			±8	LSB
Full-Scale Error	VFSE	VSS = 0.0 V			±8	LSB
Min-Scale Tempco	TCVZSE			100		ppm/°C
Full-Scale Tempco	TCVFSE			100		ppm/°C
Linearity Matching		Adjacent DAC Matching		±1		LSB
REFERENCE
Positive Reference Input Voltage Range		Note 3	VREFL + 2.5		VDD – 2.5	V
Negative Reference Input Voltage Range		VSS = 0.0 V	0		VREFH – 2.5	V
		VSS = –5.0 V	–2.5		VREFH – 2.5	V
Reference High Input Current	IREFH	Code 000H	–1.0		+1.0	mA
Large Signal Bandwidth	BW	–3 dB, VREFH = 0 V to 2.5 V p-p		450		kHz
AMPLIFIER CHARACTERISTICS		RL = 2 kΩ, CL = 100 pF
Output Current	IOUT		–1.25		+1.25	mA
Settling Time	tS	to 0.01%, 2.5 V Step, RL = 1 kΩ		7		µs
Slew Rate	SR	10% to 90%		2.2		V/µs
LOGIC CHARACTERISTICS		TA = +25°C
Logic Input High Voltage	VINH		2.4			V
Logic Input Low Voltage	VINL	TA = +25°C			0.8	V
Logic Output High Voltage	VOH	IOH = +0.4 mA	2.4			V
Logic Output Low Voltage	VOL	IOL = –1.6 mA			0.45	V
Logic Input Current	IIN				1	µA
Input Capacitance	CIN			8		pF
LOGIC TIMING CHARACTERISTICS4		Note 5
Chip Select Write Pulsewidth	tWCS		150			ns
Write Setup	tWS	tWCS = 150 ns	0			ns
Write Hold	tWH	tWCS = 150 ns	0			ns
Address Setup	tAS		0			ns
Address Hold	tAH		0			ns
Load Setup	tLS		70			ns
Load Hold	tLH		50			ns
Write Data Setup	tWDS	tWCS = 150 ns	20			ns
Write Data Hold	tWDH	tWCS = 150 ns	0			ns
Load Data Pulsewidth	tLDW		180			ns
Reset Pulsewidth	tRESET		150			ns
Chip Select Read Pulsewidth	tRCS		170			ns
Read Data Hold	tRDH	tRCS = 170 ns	20			ns
Read Data Setup	tRDS	tRCS = 170 ns	0			ns
Data to Hi Z	tDZ	CL = 10 pF			200	ns
Chip Select to Data	tCSD	CL = 100 pF			320	ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity	PSS			100		ppm/V
Positive Supply Current	IDD			7	12	mA
Negative Supply Current	ISS	VSS = –5.0 V	–10			mA
Power Dissipation	PDISS	VSS = 0 V		60		mW
		VSS = –5 V		110		mW

NOTES

1All supplies can be varied ±5%, and operation is guaranteed. Device is tested with VDD = +4.75 V.

2For single supply operation only (VREFL = 0.0 V, VSS = 0.0 V): Due to internal offset errors, INL and DNL are measured beginning at code 2 (002 H). 3Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

4All parameters are guaranteed by design.

5All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

Specifications subject to change without notice.

REV. D

–3–

DAC8412/DAC8413
CS		tRCS		80ns
			CS
		tRDH
	tRDS							tWH
R/W				t
				WS
	tAS	tAH	R/W
A0/A1				tAS
		tDZ	ADDRESS	ADDRESS	ADDRESS	ADDRESS	ADDRESS
				ONE	TWO	THREE	FOUR
DATA	HI-Z	HI -Z					tLS	tLH
OUT		DATA VALID
	tCSD
Figure 2. Data Output (Read Timing)			LDAC
								tLDW
				tWDS
								tWDH
		tWCS	DATA IN	DATA1	DATA2	DATA3	DATA4
CS				VALID	VALID	VALID	VALID

tWS

tWH

Figure 5. Double Buffer Mode

R/W

tAS

tAH

VDD

A0/A1

VREFH

VREFL

tLH

tLDW

+ +

R2

R2

R1

tLS

C1

C1 +

D1

D1

C1

D1

C2

LDAC

VREFH

VREFL

tWDS

tWDH

N/C

VOUTB

VOUTC

N/C

R3

R3

R3

DATA IN

C2

N/C

VOUTA

VOUTD

N/C

C2

VSS

VDD

tRESET

DGND

VLOGIC

C2

RESET

RESET

CS

LDAC

A0

Figure 3. Data WRITE (Input and Output Registers) Timing

DB0

A1

DB1

R/W

80ns

R6

DB2

DB11

DB3

DB10

CS

DB4

DB9

R5

R4

R4

tWS

tWH

R1

DB5

DB8

DB6

DB7

*

R/W

ONCE PER PORT

tAS

DGND

D1

+

ADDRESS

ADDRESS

ADDRESS

ADDRESS

VSS

C1

ADDRESS

ONE

TWO

THREE

FOUR

VDD = +15V, VSS = –15V, VREFH = +10V, VREFL = 0V

tLS

tLH

R1 = 10 , R2 = 100 , R3 = 5k , R4 = 10k , R5 = 100k ,

R6 = 47 FOR LCC, R6 = 100 FOR DIP

LDAC

C1 = 4.7 F (ONCE PER PORT), C2 = 0.01 F (EACH DEVICE)

D1 = 1N4001 OR EQUIVALENT (ONCE PER PORT)

tWDS

tWDH

Figure 6. Burn-In Diagram

DATA IN

DATA1

DATA2

DATA3

DATA4

VALID

VALID

VALID

VALID

Figure 4. Single Buffer Mode

–4–

REV. D

DAC8412/DAC8413

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

VSS to VDD . . . . . . . . . . . . . . . . . . . . . . .	. . . . –0.3 V, +33.0 V
VSS to VLOGIC . . . . . . . . . . . . . . . . . . . . . .	. . . –0.3 V, +33.0 V
VLOGIC to DGND . . . . . . . . . . . . . . . . . .	. . . . –0.3 V, +7.0 V
VSS to VREFL . . . . . . . . . . . . . . . . . . . . . . .	. –0.3 V, +VSS–2.0 V
VREFH to VDD . . . . . . . . . . . . . . . . . . . . . .	. . . +2.0 V, +33.0 V
VREFH to VREFL . . . . . . . . . . . . . . . . . . . . .	. . . +2.0 V, VSS–VDD
Current into Any Pin 4 . . . . . . . . . . . . . .	. . . . . . . . . . ±15 mA
Digital Input Voltage to DGND . . . . .	–0.3 V, VLOGIC +0.3 V
Digital Output Voltage to DGND . . . . . .	. . . . –0.3 V, +7.0 V
Operating Temperature Range	–40°C to +85°C
ET, FT, EP, FP, FPC . . . . . . . . . . . . .
AT, BT, BTC . . . . . . . . . . . . . . . . . . .	. . –55°C to +125°C
Dice Junction Temperature . . . . . . . . . . .	. . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . .	. . –65°C to +150°C
Power Dissipation Package . . . . . . . . . . .	. . . . . . . . 1000 mW
Lead Temperature (Soldering, 60 sec) . .	. . . . . . . . . . +300°C

Thermal Resistance

Package Type	JA*	JC	Units
28-Lead Plastic DIP (P)	48	22	°C/W
28-Lead Hermetic Leadless Chip Carrier (TC)	70	28	°C/W
28-Lead Plastic Leaded Chip Carrier (PC)	63	25	°C/W

*θJA is specified for worst-case mounting conditions, i. e., θJA is specified for device in socket.

ORDERING INFORMATION1, 2

INL	Military3 Temperature	Extended Industrial3 Temperature	Package	Package
(LSB)	–55 C to +125 C	–40 C to +85 C	Description	Option
±1		DAC8412FPC	PLCC	P-28A
±1.5	DAC8412BTC/883		LCC	E-28A
0.5		DAC8412EP	Plastic DIP	N-28
±1		DAC8412FP	Plastic DIP	N-28
±1		DAC8413FPC	PLCC	P-28A
±1.5	DAC8413BTC/883		LCC	E-28A
±0.5		DAC8413EP	Plastic DIP	N-28
±1		DAC8413FP	Plastic DIP	N-28

NOTES

1Die Size 0.225 × 0.165 inches, 37,125 sq. mils (5.715 × 4.191 mm, 23.95 sq. mm). Substrate should be connected to VDD; Transistor Count = 2595. 2Burn-in is available on extended industrial temperature range parts in cerdip.

3A complete /883 data sheet is available. For availability and burn-in information, contact your local sales office.

CAUTION

1.Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation at or above this specification is not implied. Exposure to the above maximum rating conditions for extended periods may affect device reliability.

2.Digital inputs and outputs are protected, however, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam or packaging at all times until ready to use. Use proper antistatic handling procedures.

3.Remove power before inserting or removing units from their sockets.

4.Analog outputs are protected from short circuit to ground or either supply.

WARNING!

ESD SENSITIVE DEVICE

REV. D

–5–