Analog Devices DAC8043AFS, DAC8043AFRU, DAC8043AFP, DAC8043AES, DAC8043AEP Datasheet

a		12-Bit Serial Input
		Multiplying D/A Converter
		DAC8043A

FEATURES

Compact SO-8 and TSSOP Packages True 12-Bit Accuracy

5 V Operation @ <10 A

Fast 3-Wire Serial Input

Fast 1 s Settling Time

2.4 MHz 4-Quadrant Multiply BW Pin-for-Pin Upgrade for DAC8043 Standard and Rotated Pinout

APPLICATIONS

Ideal for PLC Applications in Industrial Control Programmable Amplifiers and Attenuators Digitally Controlled Calibration and Filters Motion Control Systems

FUNCTIONAL BLOCK DIAGRAM

VDD	DAC8043A	RFB
VREF	DAC	IOUT
	12
LD	DAC REG
	12
CLK	12-BIT SHIFT	GND
SRI	REGISTER

GENERAL DESCRIPTION

The DAC8043A is an improved high accuracy 12-bit multiplying digital-to-analog converter in space-saving 8-lead packages. Featuring serial input, double buffering and excellent analog performance, the DAC8043A is ideal for applications where PC board space is at a premium. Improved linearity and gain error performance permit reduced parts count through the elimination of trimming components. Separate input clock and load DAC control lines allow full user control of data loading and analog output.

The circuit consists of a 12-bit serial-in/parallel-out shift register, a 12-bit DAC register, a 12-bit CMOS DAC and control logic. Serial data is clocked into the input register on the rising edge of the CLOCK pulse. When the new data word has been clocked in, it is loaded into the DAC register with the LD input pin. Data in the DAC register is converted to an output current by the D/A converter.

Consuming only 10 A from a single 5 V power supply, the DAC8043A is the ideal low power, small size, high performance solution to many application problems.

The DAC8043A is specified over the extended industrial (–40°C to +85°C) temperature range. DAC8043A is available in plastic DIP, and the low profile 1.75 mm height SO-8 surface mount packages. The DAC8043AFRU is available for ultracompact applications in a thin 1.1 mm TSSOP-8 package.

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

0.5

0.4TA = +25 C, +85 C, –40 C

VDD = +5V

	0.3	VREF = –10V
	0.2
– LSB	0.1
	0
INL	–0.1
	–0.2
	–0.3
	–0.4
	–0.5	512		1536		2560		3584
	0		1024		2048		3072		4096
					CODE

Figure 1. Integral Nonlinearity Error vs. Code

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Fax: [phone]	© Analog Devices, Inc., 2000

DAC8043A–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS (@ VDD = 5 V, VREF = 10 V, –40 C < TA < +85 C, unless otherwise noted.)

Parameter	Symbol	Condition	E Grade	F Grade	Unit
STATIC PERFORMANCE
Resolution	N		12	12	Bits
Relative Accuracy	INL		±0.5	±1.0	LSB max
Differential Nonlinearity	DNL	All Grades Monotonic to 12 Bits	±0.5	±1.0	LSB max
Gain Error1	GFSE	TA = 25°C, Data = FFFH	±1.0	±2.0	LSB max
		TA = –40°C, +85°C, Data = FFFH	±2.0	±2.0	LSB max
Gain Tempco2	TCGFS	IOUT Pin Measured	±5	±5	ppm/°C max
Output Leakage Current	ILKG	Data = 000H, IOUT Pin Measured	±5	±5	nA max
Zero-Scale Error3		TA = –40°C, +85°C, Data = 000H, IOUT Pin Measured	±25	±25	nA max
	IZSE	Data = 000H	0.03	0.03	LSB max
		TA = –40°C, +85°C, Data = 000H	0.15	0.15	LSB max
REFERENCE INPUT		Absolute Tempco < 50 ppm/°C			kΩ min/max
Input Resistance	RREF		7/15	7/15
Input Capacitance2	CREF		5	5	pF typ
ANALOG OUTPUT
Output Capacitance2	COUT	Data = 000H	25	25	pF typ
		Data = FFFH	30	30	pF typ
DIGITAL INPUTS
Digital Input Low	VIL		0.8	0.8	V max
Digital Input High	VIH		2.4	2.4	V min
Input Leakage Current	IIL	VLOGIC = 0 V to 5 V	0.001/± 1	0.001/± 1	µA typ/max
Input Capacitance2	CIL	VLOGIC = 0 V	10	10	pF max
INTERFACE TIMING2, 4
Data Setup	tDS		10	10	ns min
Data Hold	tDH		5	5	ns min
Clock Width High	tCH		25	25	ns min
Clock Width Low	tCL		25	25	ns min
Load Pulsewidth	tLD		25	25	ns min
LSB CLK to LD DAC	tASB		0	0	ns min
AC CHARACTERISTICS1, 2		To ±0.01% of Full Scale, Ext Op Amp OP42			µs max
Output Current Settling Time	tS		1	1
DAC Glitch	Q	Data = 000H to FFFH to 000H, VREF = 0 V	20	20	nVs max
Feedthrough (VOUT/VREF)	FT	VREF = 20 V p-p, Data = 000H, f = 10 kHz	1	1	mV p-p
Total Harmonic Distortion	THD	VREF = 6 V rms, Data = FFFH, f = 1 kHz	–85	–85	dB typ
Output Noise Density5	en	10 Hz to 100 kHz Between RFB and IOUT	17	17	nV/√Hz max
Multiplying Bandwidth	BW	–3 dB, VOUT/VREF, VREF = 100 mV rms, Data = FFFH	2.4	2.4	MHz typ
SUPPLY CHARACTERISTICS
Power Supply Range	VDD RANGE		4.5/5.5	4.5/5.5	V min/max
Positive Supply Current	IDD	VLOGIC = 0 V or VDD	10	10	µA max
Power Dissipation	PDISS	VLOGIC = 0 V or VDD	50	50	µW max
Power Supply Sensitivity	PSS	∆VDD = ±5%	0.002	0.002	%/% max

NOTES

1Using internal feedback resistor RFB, see Figure 19 test circuit with VREF = 10 V.

2These parameters are guaranteed by design and not subject to production testing.

3Calculated from worst case RREF: IZSE(LSB) = (RREF × ILKG × 4096)/VREF.

4All input control signals are specified with tR = tF = 2 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

5Calculation from en = √4KTRB where: K = Boltzmann Constant (J/°K), R = Resistance (Ω), T = Resistor Temperature (°K), B = 1 Hz Bandwidth.

Specifications subject to change without notice.

–2–

REV. A

DAC8043A

ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . .	. . . . . –0.3 V, +8 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . ±18 V
RFB to GND . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . ±18 V
Logic Inputs to GND . . . . . . . . . . . . . .	–0.3 V, VDD + 0.3 V
VIOUT to GND . . . . . . . . . . . . . . . . . . .	–0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . .	. . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . .	. (TJ max – TA)/θJA
Thermal Resistance θJA	103°C/W
8-Lead Plastic DIP Package (N-8) . . . . .
8-Lead SOIC Package (SO-8) . . . . . . . .	. . . . . . . 158°C/W
TSSOP-8 Package (RU-8) . . . . . . . . . . .	. . . . . . . 240°C/W
Maximum Junction Temperature (TJ max)	. . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . .	. – 40°C to +85°C
Storage Temperature Range . . . . . . . . . . .	. –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . .	. . . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

	INL		Package	Package
Model	(LSB)	Temp	Description	Option
DAC8043AEP	± 0.5	–40/+85°C	8-Lead P-DIP	N-8
DAC8043AES	± 0.5	–40/+85°C	8-Lead SOIC	SO-8
DAC8043A1ES	± 0.5	–40/+85°C	8-Lead SOIC	SO-8
DAC8043AFP	± 1.0	–40/+85°C	8-Lead P-DIP	N-8
DAC8043AFS	± 1.0	–40/+85°C	8-Lead SOIC	SO-8
DAC8043A1FS	± 1.0	–40/+85°C	8-Lead SOIC*	SO-8
DAC8043AFRU	± 1.0	–40/+85°C	TSSOP-8	RU-8

NOTES

The DAC8043A contains 346 transistors. The die size measures 70.3 mil × 57.1 mil, 4014 sq mil.

*The DAC8043A1ES and DAC8043A1FS have a rotated pinout.

TSSOP-8 Package Branding:

Line 1: yww (data code: year, work week). Line 2: 8043A.

		PIN FUNCTION DESCRIPTIONS
#(*)	Name	Function
1(7)	VREF	DAC Reference Input Pin. Establishes DAC full-
		scale voltage. Constant input resistance versus
		code.
2 (8)	RFB	Internal Matching Feedback Resistor. Connect
		to external op amp output.
3 (1)	IOUT	DAC Current Output, full-scale output 1 LSB
		less than reference input voltage –VREF.
4 (2)	GND	Analog and Digital Ground.
5 (3)	LD	Load Strobe, Level-Sensitive Digital Input.
		Transfers shift-register data to DAC register
		while active low. See truth table for operation.
6 (4)	SRI	12-Bit Serial Register Input, data loads directly
		into the shift register MSB first. Extra leading
		bits are ignored.
7 (5)	CLK	Clock Input, positive-edge clocks data into shift
		register.
8 (6)	VDD	Positive Power Supply Input. Specified range of
		operation 5 V ± 10%.

*Note Pin numbers in parenthesis represent the rotated pinout of the DAC8043A1ES and DAC8043A1FS models.

DAC8043AE/F PIN CONFIGURATIONS

											VREF						VDD
												1				8
											RFB						CLK
												2	TOP VIEW			7
							1	8
											IOUT						SRI
	1	8										3	(Not to Scale)			6
							4	5			GND	4				5	LD
	4	5
	TSSOP-8						SO-8						PDIP-8
	DAC8043A					DAC8043A							DAC8043A
		FRU					ES/FS						EP/FP

DAC8043A1E AND DAC8043A1F PIN CONFIGURATION

(Rotated Pinout)

IOUT						RFB
	1				8
						VREF
GND	2	TOP VIEW			7
LD						VDD
	3	(Not to Scale)			6
SRI						CLK
	4				5

SO-8

DAC8043A1ES

DAC8043A1FS

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the DAC8043A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. A

–3–