Analog Devices DAC8562GBC, DAC8562FS, DAC8562FP, DAC8562EP Datasheet

a	+5 Volt, Parallel Input
	Complete 12-Bit DAC

FEATURES Complete 12-Bit DAC

No External Components

Single +5 Volt Operation

1 mV/Bit with 4.095 V Full Scale True Voltage Output, 65 mA Drive

Very Low Power –3 mW

APPLICATIONS

Digitally Controlled Calibration

Servo Controls

Process Control Equipment

PC Peripherals

GENERAL DESCRIPTION

The DAC8562 is a complete, parallel input, 12-bit, voltage output DAC designed to operate from a single +5 volt supply. Built using a CBCMOS process, these monolithic DACs offer the user low cost, and ease-of-use in +5 volt only systems.

Included on the chip, in addition to the DAC, is a rail-to-rail amplifier, latch and reference. The reference (REFOUT) is trimmed to 2.5 volts, and the on-chip amplifier gains up the DAC output to 4.095 volts full scale. The user needs only supply a +5 volt supply.

The DAC8562 is coded straight binary. The op amp output swings from 0 to +4.095 volts for a one millivolt per bit resolution, and is capable of driving ±5 mA. Built using low tempera- ture-coefficient silicon-chrome thin-film resistors, excellent linearity error over temperature has been achieved as shown below in the linearity error versus digital input code plot.

Digital interface is parallel and high speed to interface to the fastest processors without wait states. The interface is very sim-

ple requiring only a single CE signal. An asynchronous CLR input sets the output to zero scale.

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

DAC8562

FUNCTIONAL BLOCK DIAGRAM

	REFOUT	VDD
	DAC-8562
REF	12-BIT	VOUT
	DAC

12

AGND

DAC REGISTER

12

DGND CE

DATA

CLR

The DAC8562 is available in two different 20-pin packages, plastic DIP and SOL-20. Each part is fully specified for operation over –40°C to +85°C, and the full +5 V ± 5% power supply range.

For MIL-STD-883 applications, contact your local ADI sales office for the DAC8562/883 data sheet which specifies operation over the –55°C to +125°C temperature range.

	1
	0.75		VDD = +5V
			TA = –55°C, +25°C, +125°C
LSB
	0.5
—				–55°C
	0.25
ERROR
	0
LINEARITY	–0.25
	–0.5
				+25°C & +125°C
	–0.75
	–1
	0	1024	2048	3072	4096
		DIGITAL INPUT CODE — Decimal

Figure 1. Linearity Error vs. Digital Input Code Plot

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: [phone] Fax: [phone]

DAC8562–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS (@ VDD = +5.0 6 5%, RS = No Load, –408C ≤ TA ≤ +858C, unless otherwise noted)

Parameter	Symbol	Condition	Min	Typ	Max	Units
STATIC PERFORMANCE
Resolution	N	Note 2	12	±1/4		Bits
Relative Accuracy	INL	E Grade	–1/2		+1/2	LSB
		F Grade	–1	±3/4	+1	LSB
Differential Nonlinearity	DNL	No Missing Codes	–1	±3/4	+1	LSB
Zero-Scale Error	VZSE	Data = 000H		+1/2	+3	LSB
Full-Scale Voltage	VFS	Data - FFFH3
		E Grade	4.087	4.095	4.103	V
		F Grade	4.079	4.095	4.111	V
Full-Scale Tempco	TCVFS	Notes 3, 4		±16		ppm/°C
ANALOG OUTPUT			±5	±7
Output Current	IOUT	Data = 800H				mA
Load Regulation at Half Scale	LDREG	RL = 402 Ω to ∞, Data = 800H		1	3	LSB
Capacitive Load	CL	No Oscillation4		500		pF
REFERENCE OUTPUT
Output Voltage	VREF		2.484	2.500	2.516	V
Output Source Current	IREF	Note 5	5	7		mA
Line Rejection	LNREJ				0.08	%/V
Load Regulation	LDREG	IREF = 0 to 5 mA			0.1	%/mA
LOGIC INPUTS
Logic Input Low Voltage	VIL				0.8	V
Logic Input High Voltage	VIH		2.4			V
Input Leakage Current	IIL				10	μA
Input Capacitance	CIL	Note 4			10	pF
INTERFACE TIMING SPECIFICATIONS1, 4
Chip Enable Pulse Width	tCEW		30			ns
Data Setup	tDS		30			ns
Data Hold	tDH		10			ns
Clear Pulse Width	tCLRW		20			ns
AC CHARACTERISTICS4		To ±1 LSB of Final Value				μs
Voltage Output Settling Time6	tS			16
Digital Feedthrough				35		nV sec
SUPPLY CHARACTERISTICS
Positive Supply Current	IDD	VIH = 2.4 V, VIL = 0.8 V		3	6	mA
Power Dissipation	PDISS	VIL = 0 V, VDD = +5 V		0.6	1	mA
		VIH = 2.4 V, VIL = 0.8 V		15	30	mW
		VIL = 0 V, VDD = +5V		3	5	mW
Power Supply Sensitivity	PSS	VDD = ±5%		0.002	0.004	%/%

NOTES

1All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 21 LSB = 1 mV for 0 to +4.095 V output range.

3Includes internal voltage reference error.

4These parameters are guaranteed by design and not subject to production testing.

5Very little sink current is available at the REFOUT pin. Use external buffer if setting up a virtual ground.

6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region.

Specifications subject to change without notice.

–2–

REV. A

							DAC8562
	(@ VDD = +5.0 V 6 5%, RL = No Load, TA = +258C, applies to part number DAC8562GBC only,
WAFER TEST LIMITS unless otherwise noted)
Parameter		Symbol	Condition	Min	Typ	Max		Units
STATIC PERFORMANCE					±3/4
Relative Accuracy		INL		–1		+1		LSB
Differential Nonlinearity		DNL	No Missing Codes	–1	±3/4	+ 1		LSB
Zero-Scale Error		VZSE	Data = 000H		+1/2	+3		LSB
Full-Scale Voltage		VFS	Data = FFFH	4.085	4.095	4.105		V
Reference Output Voltage		VREF		2.490	2.500	2.510		V
LOGIC INPUTS
Logic Input Low Voltage		VIL				0.8		V
Logic Input High Voltage		VIH		2.4				V
Input Leakage Current		IIL				10		μA
SUPPLY CHARACTERISTICS
Positive Supply Current		IDD	VIH = 2.4 V, VIL = 0.8 V		3	6		mA
Power Dissipation		PDISS	VIL = 0 V, VDD = +5 V		0.6	1		mA
			VIH = 2.4 V, VIL = 0.8 V		15	30		mW
			VIL = 0 V, VDD = +5 V		3	5		mW
Power Supply Sensitivity		PSS	VDD = ±5%		0.002	0.004		%/%

NOTE

1Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

ABSOLUTE MAXIMUM RATINGS*
VDD to DGND and AGND . . . . . . . . . . . .	. . . . –0.3 V, +10 V
Logic Inputs to DGND . . . . . . . . . . . . . . .	–0.3 V, VDD + 0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . . . . .	–0.3 V, VDD + 0.3 V
VREFOUT to AGND . . . . . . . . . . . . . . . . . .	–0.3 V, VDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . .	. . . . . . –0.3 V, VDD
IOUT Short Circuit to GND . . . . . . . . . . . .	. . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . .	. . (TJ max – TA)/uJA
Thermal Resistance uJA	74°C/W
20-Pin Plastic DIP Package (P) . . . . . . .
20-Lead SOIC Package (S) . . . . . . . . . .	. . . . . . . . . 89°C/W
Maximum Junction Temperature (TJ max)	. . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . .	. . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . .	. . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . .	. . . . . . . . . +300°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

	1	tCEW
	CE
	0	tDS	tDH
	1
	DB11–0	DATA VALID
	0
	1		tCLRW
	CLR
	0
	FS		±1 LSB
	VOUT
			ERROR BAND
	ZS	tS	tS
		Figure 2. Timing Diagram
		Table I. Control Logic Truth Table
	CE	CLR	DAC Register Function
	H	H	Latched
	L	H	Transparent
	− +	H	Latched with New Data
	X	L	Loaded with All Zeros
	H	− +	Latched All Zeros

− + Positive Logic Transition; X Don't Care.

CAUTION

ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are inserted.

WARNING!

ESD SENSITIVE DEVICE

REV. A

–3–

DAC8562

			PIN CONFIGURATIONS
		20-Pin P-DIP						SOL-20
			(N-20)					(R-20)
DB3								1
	1				20	VDD
DB4	2				19	DB2
						DB1
DB5	3				18			DAC-8562
						DB0		TOP VIEW
DB6	4				17
			DAC-8562					(Not to Scale)
DB7	5				16	CE
			TOP VIEW
DB8	6		(Not to Scale)		15	CLR
DB9						REFOUT
	7				14
DB10
	8				13	VOUT
DB11						AGND
	9				12
DGND	10				11	NC

NC = NO CONNECT

ORDERING GUIDE

		INL			Temperature		Package
Model		(LSB)			Range		Option
DAC8562EP		±1/2			–40°C to +85°C		N-20
DAC8562FP		±1			–40°C to +85°C		N-20
DAC8562FS		±1			–40°C to +85°C		R-20
DAC8562GBC		±1			+25°C		Dice
	DICE CHARACTERISTICS
		AGND			DGND	DB11
	12				10	9
VOUT	13					8	DB10
REFOUT	14					7	DB9
CLR	15					6	DB8
	16					5	DB7
CE
DB0	17					4	DB6
DB1	18					3	DB5
	19		20		1	2
		DB2	VDD		DB3	DB4

SUBSTRATE IS COMMON WITH VDD.

TRANSISTOR COUNT: 524

DIE SIZE: 0.70 X 0.105 INCH; 7350 SQ MILS

Table II. Nominal Output Voltage vs. Input Code

Binary	Hex	Decimal	Output (V)
0000 0000 0000	000	0	0.000 Zero Scale
0000 0000 0001	001	1	0.001
0000 0000 0010	002	2	0.002
0000 0000 1111	00F	15	0.015
0000 0001 0000	010	16	0.016
0000 1111 1111	0FF	255	0.255
0001 0000 0000	100	256	0.256
0001 1111 1111	1FF	511	0.511
0010 0000 0000	200	512	0.512
0011 1111 1111	3FF	1023	1.023
0100 0000 0000	400	1024	1.024
0111 1111 1111	7FF	2047	2.047
1000 0000 0000	800	2048	2.048	Half Scale
1100 0000 0000	C00	3072	3.072
1111 1111 1111	FFF	4095	4.095	Full Scale

					PIN DESCRIPTIONS
Pin		Name				Description
20		VDD				Positive supply. Nominal value
						+5 volts, ±5%.
1-9	DB0-DB11					Twelve Binary Data Bit inputs. DB11
17-19						is the MSB and DB0 is the LSB.
16						Chip Enable. Active low input.
		CE
15						Active low digital input that clears the
		CLR
						DAC register to zero, setting the DAC
						to minimum scale.
8		DGND				Digital ground for input logic.
12		AGND				Analog Ground. Ground reference for
						the internal bandgap reference voltage,
						the DAC, and the output buffer.
13		VOUT				Voltage output from the DAC. Fixed
						output voltage range of 0 V to 4.095 V
						with 1 mV/LSB. An internal tempera-
						ture stabilized reference maintains a
						fixed full-scale voltage independent of
						time, temperature and power supply
						variations.
14		REFOUT				Nominal 2.5 V reference output volt-
						age. This node must be buffered if re-
						quired to drive external loads.
11		NC				No Connection. Leave pin floating.

–4–

REV. A

DAC8562

OPERATION

The DAC8562 is a complete ready to use 12-bit digital-to- analog converter. Only one +5 V power supply is necessary for operation. It contains a voltage-switched, 12-bit, laser-trimmed digital-to-analog converter, a curvature-corrected bandgap reference, a rail-to-rail output op amp, and a DAC register. The parallel data interface consists of 12 data bits, DB0–DB11, and a active low CE strobe. In addition, an asynchronous CLR pin

will set all DAC register bits to zero causing the VOUT to become zero volts. This function is useful for power on reset or system failure recovery to a known state.

D/A CONVERTER SECTION

The internal DAC is a 12-bit voltage-mode device with an output that swings from AGND potential to the 2.5 volt internal bandgap voltage. It uses a laser trimmed R-2R ladder which is switched by N channel MOSFETs. The output voltage of the DAC has a constant resistance independent of digital input code. The DAC output (not available to the user) is internally connected to the rail-to-rail output op amp.

AMPLIFIER SECTION

The internal DAC’s output is buffered by a low power consumption precision amplifier. This low power amplifier contains a differential PNP pair input stage which provides low offset voltage and low noise, as well as the ability to amplify the zeroscale DAC output voltages. The rail-to-rail amplifier is configured in a gain of 1.6384 (= 4.095 V/2.5 V) in order to set the 4.095 volt full-scale output (1 mV/LSB). See Figure 3 for an equivalent circuit schematic of the analog section.

REFOUT
2.5V	VOLTAGE SWITCHED 12-BIT
BANDGAP	R-2R D/A CONVERTER		RAIL-TO-RAIL
			OUTPUT
REFERENCE
		2R	AMPLIFIER
		R	VOUT
	BUFFER
			R2
		2R
		R	R1
		2R	AV = 4.096/2.5
			= 1.636V/V
	SPDT	2R
	N ch FET
	SWITCHES	2R

Figure 3. Equivalent DAC8562 Schematic of Analog Portion

The op amp has a 16 μs typical settling time to 0.01%. There are slight differences in settling time for negative slewing signals versus positive. See the oscilloscope photos in the Typical Performances section of this data sheet.

OUTPUT SECTION

The rail-to-rail output stage of this amplifier has been designed to provide precision performance while operating near either power supply. Figure 4 shows an equivalent output schematic of the rail-to-rail amplifier with its N channel pull down FETs that will pull an output load directly to GND. The output sourcing

current is provided by a P channel pull-up device that can supply GND terminated loads, especially important at the –5% supply tolerance value of 4.75 volts.

VDD

P-CH

VOUT

N-CH

AGND

Figure 4. Equivalent Analog Output Circuit

Figures 5 and 6 in the typical performance characteristics section provide information on output swing performance near ground and full scale as a function of load. In addition to resistive load driving capability, the amplifier has also been carefully designed and characterized for up to 500 pF capacitive load driving capability.

REFERENCE SECTION

The internal 2.5 V curvature-corrected bandgap voltage reference is laser trimmed for both initial accuracy and low temperature coefficient. The voltage generated by the reference is available at the REFOUT pin. Since REFOUT is not intended to drive external loads, it must be buffered–refer to the applications section for more information. The equivalent emitter follower output circuit of the REFOUT pin is shown in Figure 3.

Bypassing the REFOUT pin is not required for proper operation. Figure 7 shows broadband noise performance.

POWER SUPPLY

The very low power consumption of the DAC8562 is a direct result of a circuit design optimizing use of the CBCMOS process. By using the low power characteristics of the CMOS for the logic, and the low noise, tight matching of the complementary bipolar transistors, good analog accuracy is achieved.

For power-consumption sensitive applications it is important to note that the internal power consumption of the DAC8562 is strongly dependent on the actual logic-input voltage-levels present on the DB0–DB11, CE and CLR pins. Since these inputs are standard CMOS logic structures, they contribute static power dissipation dependent on the actual driving logic VOH and VOL voltage levels. The graph in Figure 9 shows the effect on total DAC8562 supply current as a function of the actual value of input logic voltage. Consequently for optimum dissipation use of CMOS logic versus TTL provides minimal dissipation in the static state. A VINL = 0 V on the DB0–DB11 pins provides the lowest standby dissipation of 600 μA with a +5 V power supply.

REV. A

–5–