Analog Devices DAC8222GP, DAC8222FS, DAC8222FP, DAC8222EW, DAC8222BTC Datasheet

a		Dual 12-Bit Double-Buffered
		Multiplying CMOS D/A Converter
		DAC8222

FEATURES

Two Matched 12-Bit DACs on One Chip

Direct Parallel Load of All 12 Bits for High Data Throughput

Double-Buffered Digital Inputs

12-Bit Endpoint Linearity ( 1/2 LSB) Over Temperature

+5 V to +15 V Single Supply Operation DACs Matched to 1% Max Four-Quadrant Multiplication Improved ESD Resistance

Packaged in a Narrow 0.3" 24-Lead DIP and 0.3" 24Lead SOL Package

Available in Die Form

APPLICATIONS

Automatic Test Equipment

Robotics/Process Control/Automation

Digital Gain/Attenuation Control

Ideal for Battery-Operated Equipment

GENERAL DESCRIPTION

The DAC8222 is a dual 12-bit, double-buffered, CMOS digital- to-analog converter. It has a 12-bit wide data port that allows a 12-bit word to be loaded directly. This achieves faster throughput time in stand-alone systems or when interfacing to a 16-bit processor. A common 12-bit input TTL/CMOS compatible data port is used to load the 12-bit word into either of the two DACs. This port, whose data loading is similar to that of a RAM’s write cycle, interfaces directly with most 12-bit and 16-bit bus systems. (See DAC8248 for a complete 8-bit data bus interface product.) A common bus allows the DAC8222 to be packaged in a narrow 24-lead 0.3" DIP and save PCB space.

The DAC is controlled with two signals, WR and LDAC. With logic low at these inputs, the DAC registers become transparent. This allows direct unbuffered data to flow directly to either DAC output selected by DAC A/DAC B. Also, the DAC’s

FUNCTIONAL DIAGRAM

double-buffered digital inputs will allow both DACs to be simultaneously updated.

DAC8222’s monolithic construction offers excellent DAC-to- DAC matching and tracking over the full operating temperature range. The chip consists of two thin-film R-2R resistor ladder networks, four 12-bit registers, and DAC control logic circuitry. The device has separate reference-input and feedback resistors for each DAC and operates on a single supply from +5 V to +15 V. Maximum power dissipation at +5 V using zero or VDD logic levels is less than 0.5 mW.

The DAC8222 is manufactured with highly stable thin-film resistors on an advanced oxide-isolated, silicon-gate, CMOS technology. Improved latch-up resistant design eliminates the need for external protective Schottky diodes.

REV. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Fax: [phone]	© Analog Devices, Inc., 2000

DAC8222–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS (@ VDD = +5 V or +15 V, VREF A = VREF B = +10 V, VOUT A = VOUT B = 0 V; AGND = DGND = 0 V; TA = Full Temperature Range Specified in Absolute Maximum Ratings; unless otherwise noted. Specifications apply for DAC A and DAC B.)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

STATIC ACCURACY

Resolution

N

12

± 1/2

Bits

Relative Accuracy

INL

Endpoint Linearity Error DAC8222A/E/G

LSB

DAC8222F/H

± 1

LSB

Differential Nonlinearity

DNL

All Grades are Guaranteed Monotonic

± 1

LSB

Full-Scale Gain Error1

GFSE

DAC8222A/E

± 1

LSB

DAC8222G

± 2

LSB

Gain Temperature Coefficient

DAC8222F/H

± 4

LSB

± 2

± 5

ppm/°C

∆Gain/∆Temperature

TCGFS

(Notes 2, 7)

Output Leakage Current

TA = +25°C

± 5

± 10

IOUT A (Pin 2),

ILKG

All Digital Inputs =

nA

IOUT B (Pin 24)

0000 0000 0000

TA = Full Temp. Range

± 50

nA

Input Resistance

kΩ

(VREF A, VREF B)

RREF

(Note 9)

8

11

15

Input Resistance Match

∆RREF

± 0.2

± 1

%

RREF

DIGITAL INPUTS

VDD = +5 V

2.4

V

Digital Input High

VINH

VDD = +15 V

13.5

V

Digital Input Low

VINL

VDD = +5 V

0.8

V

VDD = +15 V

1.5

V

Input Current

IIN

VIN = 0 V or VDD

TA = +25°C

± 0.001 ± 1

µA

Input Capacitance2

and VINL or VINH

TA = Full Temp. Range

± 10

µA

CIN

DB0–DB11

10

pF

WR, LDAC, DAC A/DAC B

15

pF

POWER SUPPLY

All Digital Inputs VINL or VINH

2

mA

Supply Current

IDD

DC Power Supply

All Digital Inputs 0 V or VDD

10

100

µA

∆VDD = ± 5%

0.002

%/%

Rejection Ratio

PSRR

(∆Gain/∆VDD)

AC PERFORMANCE CHARACTERISTICS2

Propagation Delay4, 5

tPD

TA = +25°C

350

ns

Current Settling Time5, 6

tS

TA = +25°C

1

µs

Output Capacitance

CO

Digital Inputs = All 0s

90

pF

COUT A, COUT B

90

pF

Digital Inputs = All 1s

120

pF

COUT A, COUT B

120

pF

AC Feedthrough at

FTA

VREF A to IOUT A; VREF A = 20 V p-p;

–70

dB

IOUT A or IOUT B

f = 100 kHz; TA = +25°C

–70

dB

VREF B to IOUT B; VREF B

= 20 V p-p;

–70

dB

FTB

f = 100 kHz; TA = +25°C

–70

dB

SWITCHING CHARACTERISTICS2, 3

VDD = +5 V

–55°C to +125°C

VDD = +15 V

+25°C

–40°C to +85°C8

All Temps10

DAC Select to

tAS

150

180

210

60

ns min

Write Set-Up Time

0

0

0

0

ns min

DAC Select to

tAH

Write Hold Time

80

100

120

60

ns min

LDAC to

tLS

Write Set-Up Time

20

20

20

20

ns min

LDAC to

tLH

Write Hold Time

220

240

260

100

ns min

Data Valid to

tDS

Write Set-Up Time

0

0

0

10

ns min

Data Valid to

tDH

Write Hold Time

130

160

170

90

ns min

Write Pulse Width

tWR

LDAC Pulse Width

tLWD

100

120

130

60

ns min

NOTES

1Measured using internal RFB A and RFB B. Both DAC digital inputs = 1111 1111 1111. 2Guaranteed and not tested.

3See timing diagram.

4From 50% of digital input to 90% of final analog output current.

VREF A = VREF B = +10 V; OUT A, OUT B load = 100 Ω, CEXT = 13 pF. 5WR, LDAC = 0 V; DB0–DB11 = 0 V to VDD or VDD to 0 V.

6Settling time is measured from 50% of the digital input change to where the output voltage settles within 1/2 LSB of full scale.

7Gain TC is measured from +25°C to TMIN or from +25°C to TMAX.

8These limits apply for the commercial and industrial grade products.

9Absolute temperature coefficient is approximately +50 ppm/°C.

10These limits also apply as typical values for VDD = +12 V with +5 V CMOS logic levels and TA = +25°C.

Specifications subject to change without notice.

–2–

REV. C

DAC8222

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C, unless otherwise noted.)
VDD to AGND . . . . . . . . . .	. . . . . . . .	. . . . .	. . . .	. 0 V, +17 V
VDD to DGND . . . . . . . . . .	. . . . . . . .	. . . . .	. . . .	. 0 V, +17 V
AGND to DGND . . . . . . .	. . . . . . . .	. . . –0.3 V, VDD +0.3 V
Digital Input Voltage to DGND . . . .		. . . –0.3 V, VDD +0.3 V
IOUTA, IOUTB to AGND . . .	. . . . . . . .	. . . –0.3 V, VDD +0.3 V
VREFA, VREFB to AGND . . .	. . . . . . . .	. . . . . .	. . .	. . . . . ±25 V
VRFBA, VRFBB to AGND . . .	. . . . . . . .	. . . . . .	. . .	. . . . . ±25 V
Operating Temperature Range			–55°C to +125°C
AW Version . . . . . . . . . .	. . . . . . . .	. . . . .
EW, FW, FP Versions . .	. . . . . . . .	. . . . . .	–40°C to +85°C
GP, HP, HS Versions . . .	. . . . . . . .	. . . . . .	. . 0°C to +70°C
Junction Temperature . . . .	. . . . . . . .	. . . . . .	. . .	. . . .+150°C
Storage Temperature . . . . .	. . . . . . . .	. . . . .	–65°C to +150°C
Lead Temperature (Soldering, 60 sec)		. . . . .	. . .	. . . .+300°C
Package Type	JA1	JC		Units
24-Lead Hermetic DIP (W)	69	10		°C/W
24-Lead Plastic DIP (P)	62	32		°C/W
24-Lead SOL (S)	72	24		°C/W

NOTE

1θJA is specified for worst-case mounting conditions, i.e., qJA is specified for device in socket for Cerdip, and P-DIP packages; JA is specified for device soldered to printed circuit board for SO package.

CAUTION

1.Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFB.

2.The digital control inputs are Zener-protected; however, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam at all times until ready to use.

3.Do not insert this device into powered sockets; remove power before insertion or removal.

4.Use proper antistatic handling procedures.

5.Devices can suffer permanent damage and/or reliability degradation if stressed above the limits listed under Absolute Maximum Ratings for extended periods.

PIN CONNECTIONS

24-Lead 0.3" Cerdip

24-Lead Plastic DIP 28-Terminal LCC

24-Lead SOL

NC = NO CONNECT

ORDERING GUIDE

	INL	GFSE	Temperature	Package	Package
Model	(LSB)	(LSB)	Range	Description	Option
DAC8222EW	±1/2	± 1	–40°C to +85°C	Cerdip-24	Q-24
DAC8222GP	±1/2	± 2	0°C to +70°C	P-DIP-24	N-24
DAC8222BTC/883*	±1	± 4	–55°C to +125°C	LCC-28	E-28A
DAC8222FW	±1	± 4	–40°C to +85°C	Cerdip-24	Q-24
DAC8222FP	±1	± 4	–40°C to +85°C	P-DIP-24	N-24
DAC8222FS	±1	± 4	–40°C to +85°C	SOL-24	R-24

*Consult factory for DAC8222/883 MIL-STD data sheet.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the DAC8222 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

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–3–

DAC8222

DICE CHARACTERISTICS

1.	AGND	13.	DB4
2.	IOUT A	14.	DB3
3.	RFB A	15.	DB2
4.	VREF A	16.	DB1
5.	DGND	17.	DB0 (LSB)
6.	DB11(MSB)	18.	DAC A/DAC B
7.	DB10	19.	LDAC
8.	DB9	20.	WR
9.	DB8	21.	VDD
10.	DB7	22.	VREF B
11.	DB6	23.	RFB B
12.	DB5	24.	IOUT B

Substrate (die backside) is internally connected to VDD.

DIE SIZE 0.124 × 0.132 inch, 16,368 sq. mils (3.15 × 3.55 mm, 10.56 sq. mm)

WAFER TEST LIMITS (@ VDD = +5 V or +15 V, VREF A = VREF B = +10 V, VOUT A = VOUT B = 0 V; AGND = DGND = 0 V; TA = +25 C)

			DAC8222G
Parameter	Symbol	Conditions	Limit	Units
Relative Accuracy	INL	Endpoint Linearity Error	± 1	LSB max
Differential Nonlinearity	DNL	All Grades are Guaranteed Monotonic	± 1	LSB max
Full Scale Gain Error1	GFSE	Digital Inputs = 1111 1111 1111	± 4	LSB max
Output Leakage		Digital Inputs = 0000 0000 0000	±50	nA max
(IOUT A, IOUT B)	ILKG	Pads 2 and 24
Input Resistance				kΩ max
(VREF A, VREF B)	RREF	Pads 4 and 22	8/15
Input Resistance Match	∆RREF		± 1	% max
	RREF
Digital Input High	VINH	VDD = +5 V	2.4	V min
		VDD = +15 V	13.5	V min
Digital Input Low	VINL	VDD = +5 V	0.8	V max
		VDD = +15 V	1.5	V min
Digital Input Current	IIN	VIN = 0 V or VDD; VINL or VINH	± 1	µA max
Supply Current	IDD	All Digital Inputs VINL or VINH	2
		All Digital Inputs 0 V or VDD	0.1	mA max
DC Supply Rejection	PSR	∆VDD = ±5%	0.002	%/% max
(∆Gain/∆VDD)

NOTES

1Measured using internal RFB A and RFB B.

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

–4–

REV. C

DAC8222

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 1. Channel-to-Channel Match-	Figure 2. Differential Nonlinearity	Figure 3. Differential Nonlinearity
ing (DAC A and B are Superimposed)	vs. VREF	vs. VREF

Figure 4. Nonlinearity vs. VREF

Figure 5. Nonlinearity vs. VREF

Figure 6. Nonlinearity vs. VDD

Figure 7. Nonlinearity vs. Code	Figure 8. Nonlinearity vs. Code at TA	Figure 9. Absolute Gain Error
(DAC A and B are Superimposed)	= –55°C, +25°C, +125°C for DAC A and	Changes vs. VREF
	B (All Superimposed)

REV. C

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