Analog Devices DAC8248HS, DAC8248HP, DAC8248GP, DAC8248FW, DAC8248FP Datasheet

a Dual 12-Bit (8-Bit Byte)

Double-Buffered CMOS D/A Converter

DAC8248

FEATURES

Two Matched 12-Bit DACs on One Chip 12-Bit Resolution with an 8-Bit Data Bus Direct Interface with 8-Bit Microprocessors Double-Buffered Digital Inputs

RESET to Zero Pin

12-Bit Endpoint Linearity (61/2 LSB) Over Temperature 15 V to 115 V Single Supply Operation

Latch-Up Resistant Improved ESD Resistance

Packaged in a Narrow 0.3" 24-Pin DIP and 0.3" 24-Pin SOL Package

Available in Die Form

APPLICATIONS

Multichannel Microprocessor-Controlled Systems

Robotics/Process Control/Automation

Automatic Test Equipment

Programmable Attenuator, Power Supplies, Window

Comparators

Instrumentation Equipment

Battery Operated Equipment

GENERAL DESCRIPTION

PIN CONNECTIONS

24-Pin 0.3" Cerdip (W Suffix),

24-Pin Epoxy DIP (P Suffix),

24-Pin SOL (S Suffix)

The DAC8248’s double-buffered digital inputs allow both DAC’s analog output to be updated simultaneously. This is particularly useful in multiple DAC systems where a common LDAC signal updates all DACs at the same time. A single RESET pin resets both outputs to zero.

The DAC8248 is a dual 12-bit, double-buffered, CMOS digital- to-analog converter. It has an 8-bit wide input data port that interfaces directly with 8-bit microprocessors. It loads a 12-bit word in two bytes using a single control; it can accept either a least significant byte or most significant byte first. For designs with a 12-bit or 16-bit wide data path, choose the DAC8222 or DAC8221.

The DAC8248’s monolithic construction offers excellent DAC- to-DAC matching and tracking over the full operating temperature range. The DAC consists of two thin-film R-2R resistor ladder networks, two 12-bit, two 8-bit, and two 4-bit data registers, and control logic circuitry. Separate reference input and feedback resistors are provided for each DAC. The DAC8248

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FUNCTIONAL BLOCK DIAGRAM

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: [phone] Fax: [phone]

DAC8248–SPECIFICATIONS

ELECTRICAL CHARACTERlSTICS (@ VDD = +5 V or +15 V; VREF A = VREF B = +10 V; VOUTA = VOUT B = 0 V; AGND = DGND = 0 V; TA = Full Temp Range specified in Absolute Maximum Ratings; unless otherwise noted. Specifications apply for DAC A and DAC B.)

DAC8248

Parameter

Symbol

Conditions

Min

Typ

Max

Units

STATIC ACCURACY

Resolution

N

12

±1/2

Bits

Relative Accuracy

INL

DAC8248A/E/G

LSB

DAC8248F/H

±1

LSB

Differential Nonlinearity

DNL

All Grades are Guaranteed Monotonic

±1

LSB

Full-Scale Gain Error1

GFSE

DAC8248A/E

±1

LSB

DAC8248G

±2

LSB

DAC8248F/H

±4

LSB

Gain Temperature Coefficient

±2

±5

ppm/°C

( Gain/ Temperature)

TCGFS

(Notes 2, 3)

All Digital Inputs = 0s

Output Leakage Current

ILKG

TA = +25°C

±5

±10

IOUT A (Pin 2), IOUT B (Pin 24)

TA = Full Temperature Range

±50

nA

Input Resistance (VREF A, REF B)

RREF

(Note 4)

8

11

15

kΩ

Input Resistance Match

RREF

±0.2

±1

%

RREF

DIGITAL INPUTS

Digital Input High

VINH

VDD = +5 V

2.4

V

Digital Input Low

VINL

VDD = +15 V

13.5

V

VDD = +5 V

0.8

V

VDD = +15 V

±0.001

1.5

V

Input Current (VIN = 0 V

TA = +25°C

±1

μA

or VDD and VINL or VINH)

IIN

TA = Full Temperature Range

±10

μA

Input Capacitance

CIN

DB0–DB11

10

pF

(Note 2)

WR

,

LDAC

,

DAC A

/DAC B,

LSB/MSB,

RESET

15

pF

POWER SUPPLY

Supply Current

IDD

Digital Inputs = VINL or VINH

2

mA

Digital Inputs = 0 V or VDD

10

100

μA

DC Power Supply Rejection Ratio

PSRR

VDD = ±5%

( Gain/ VDD)

0.002

%/%

AC PERFORMANCE CHARACTERISTICS2

TA = +25°C

Propagation Delay5, 6

tPD

350

ns

Output Current Setting Time6, 7

tS

TA = +25°C

1

μs

Output Capacitance

CO

Digital Inputs = All 0s

COUT A, COUT B

90

pF

Digital Inputs = All 1s

AC Feedthrough at

FTA

COUT A, COUT B

120

pF

VREF A to IOUT A; VREF A = 20 V p-p

IOUT A or IOUT B

FTB

f = 100 kHz; TA = +25°C

–70

dB

VREF B to IOUT B; VREF B = 20 V p-p

f = 100 kHz; TA = +25°C

–70

dB

–2–

REV. B

							DAC8248
Parameter		Symbol	Conditions			DAC8248		Units
Switching Characteristics					VDD = +5 V		VDD = +15 V
				+258C	–408C to +858C	–558C to +1258C	All Temps
(Notes 2, 8)					(Note 9)		(Note 10)
	/MSB Select to
LSB
Write Set-Up Time		tCBS		130	170	180	80	ns min
LSB	/MSB Select to
Write Hold Time		tCBH		0	0	0	0	ns min
DAC Select to
Write Set-Up Time		tAS		180	210	220	80	ns min
DAC Select to
Write Hold Time		tAH		0	0	0	0	ns min
LDAC to
Write Set-Up Time		tLS		120	150	160	80	ns min
LDAC to
Write Hold Time		tLH		0	0	0	0	ns min
Data Valid to
Write Set-Up Time		tDS		160	210	220	70	ns min
Data Valid to
Write Hold Time		tDH		0	0	0	10	ns min
Write Pulse Width		tWR		130	150	170	90	ns min
LDAC Pulse Width		tLWD		100	110	130	60	ns min
Reset Pulse Width		tRWD		80	90	90	60	ns min

NOTES

1Measured using internal RFB A and RFB B. Both DAC digital inputs = 1111 1111 1111. 2Guaranteed and not tested.

3Gain TC is measured from +25°C to TMIN or from +25°C to TMAX. 4Absolute Temperature Coefficient is approximately +50 ppm/°C.

5From 50% of digital input to 90% of final analog output current. VREF A = VREF B = +10 V; OUT A, OUT B load = 100 Ω, CEXT = 13 pF. 6WR, LDAC = 0 V; DB0–DB7 = 0 V to VDD or VDD to 0 V.

7Settling time is measured from 50% of the digital input change to where the output settles within 1/2 LSB of full scale. 8See Timing Diagram.

9These limits apply for the commercial and industrial grade products.

10These limits also apply as typical values for VDD = +12 V with +5 V CMOS logic levels and TA = +25°C. Specifications subject to change without notice.

Burn-In Circuit

REV. B

–3–

DAC8248

(continued from page 1)

operates on a single supply from +5 V to +15 V, and it dissipates less than 0.5 mW at +5 V (using zero or VDD logic levels). The device is packaged in a space-saving 0.3", 24-pin DIP.

The DAC8248 is manufactured with PMI’s highly stable thinfilm resistors on an advanced oxide-isolated, silicon-gate, CMOS technology. PMI’s improved latch-up resistant design eliminates the need for external protective Schottky diodes.

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C, unless otherwise noted.)

VDD to AGND . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 0 V, +17 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 0 V, +17 V
AGND to DGND . . . . . . . . . . . . . . . . . .	–0.3 V, VDD +0.3 V
Digital Input Voltage to DGND . . . . . . .	–0.3 V, VDD +0.3 V
IOUT A, IOUT B to AGND . . . . . . . . . . . . . .	–0.3 V, VDD +0.3 V
VREF A, VREF B to AGND . . . . . . . . . . . . . .	. . . . . . . . . . ±25 V
VRFB A, VRFB B to AGND . . . . . . . . . . . . . .	. . . . . . . . . . ±25 V
Operating Temperature Range	–55°C to +125°C
AW Version . . . . . . . . . . . . . . . . . . . . . .
EW, FW, FP Versions . . . . . . . . . . . . . .	. . –40°C to +85°C
GP, HP, HS Versions . . . . . . . . . . . . . . .	. . . . 0°C to +70°C
Junction Temperature . . . . . . . . . . . . . . . .	. . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . .	. –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . .	. . . . . . . . +300°C

Package Type	uJA1	uJC	Units
24-Pin Hermetic DIP (W)	69	10	°C/W
24-Pin Plastic DIP (P)	62	32	°C/W
24-Pin SOL (S)	72	24	°C/W

NOTE

1uJA specified for worst case mounting conditions, i.e., uJA is specified for device in socket for cerdip and P-DIP packages; uJA is specified for device soldered to printed circuit board for SOL package.

CAUTION

1.Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFB.

2.The digital control inputs are Zener-protected; however, permanent damage may occur on unprotected units from high energy electrostatic fields. Keep units in conductive foam at all times until ready to use.

3.Do not insert this device into powered sockets; remove power before insertion or removal.

4.Use proper antistatic handling procedures.

5.Devices can suffer permanent damage and/or reliability degradation if stressed above the limits listed under Absolute Maximum Ratings for extended periods. This is a stress rating only and functional operation at or above this specification is not implied.

ORDERING GUIDE1

	Relative
	Accuracy	Gain Error	Temperature	Package
Model	(+5 V or +15 V)	(+5 V or +15 V)	Range	Description
DAC8248AW2	±1/2 LSB	±1 LSB	–55°C to +125°C	24-Pin Cerdip
DAC8248EW	±1/2 LSB	±1 LSB	–40°C to +85°C	24-Pin Cerdip
DAC8248GP	±1/2 LSB	±2 LSB	0°C to +70°C	24-Pin Plastic DIP
DAC8248FW	±1 LSB	±4 LSB	–40°C to +85°C	24-Pin Cerdip
DAC8248HP	±1 LSB	±4 LSB	0°C to +70°C	24-Pin Plastic DIP
DAC8248FP	±1 LSB	±4 LSB	–40°C to +85°C	24-Pin Plastic DIP
DAC8248HS3	±1 LSB	±4 LSB	0°C to +70°C	24-Pin SOL

NOTES

1Burn-in is available on commercial and industrial temperature range parts in cerdip, plastic DIP, and TO-can packages. 2For devices processed in total compliance to MIL-STD-883, add/883 after part number. Consult factory for 883 data sheet. 3For availability and burn-in information on SO and PLCC packages, contact your local sales office.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the DAC8248 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. B

DAC8248

DICE CHARACTERISTICS

1.	AGND	13.	NC
2.	IOUTA	14.		DB1
3.	RFB A	15.		DB0(LSB)
4.	VREF A	16.		RESET
5.	DGND	17.				/MSB
				LSB
6.	DB7(MSB)	18.		DAC A				/DAC B
7.	DB6	19.
				LDAC
8.	DB5	20.
				WR
9.	DB4	21.		VDD
10.	DB3	22.		VREF B
11.	DB2	23.		RFB B
12.	NC	24.		IOUT B

SUBSTRATE (DIE BACKSIDE) IS INTERNALLY

CONNECTED TO VDD.

Die Size 0.124 × 0.132 inch, 16,368 sq. mils (3.15 × 3.55 mm, 10.56 sq. mm)

WAFER TEST LIMITS @ VDD = +5 V or +15 V, VREF A = VREF B = +10 V, VOUT A = VOUT B = 0 V; AGND = DGND = 0 V; TA = 258C.

			DAC8248G
Parameter	Symbol	Conditions	Limit	Units
Relative Accuracy	INL	Endpoint Linearity Error	±1	LSB max
Differential Nonlinearity	DNL	All Grades are Guaranteed Monotonic	±1	LSB max
Full-Scale Gain Error1	GFSE	Digital Inputs = 1111 1111 1111	±4	LSB max
Output Leakage		Digital Inputs = 0000 0000 0000	±50
(IOUT A, IOUT B)	ILKG	Pads 2 and 24		nA max
Input Resistance				kΩ min/kΩ max
(VREF A, VREF B)	RREF	Pads 4 and 22	8/15
VREF A, VREF B Input	RREF		±1
Resistance Match	RREF			% max
Digital Input High	VINH	VDD = +5 V	2.4	V min
Digital Input Low	VINL	VDD = +15 V	13.5	V min
		VDD = +5 V	0.8	V max
		VDD = +15 V	1.5	V max
Digital Input Current	IIN	VIN = 0 V or VDD; VINL or VINH	±1	μA max
Supply Current	IDD	All Digital Inputs VINL or VINH	2	mA max
DC Supply Rejection		All Digital Inputs 0 V or VDD	0.1	mA max
		VDD = ±5%
( Gain/ VDD)	PSR		0.002	%/% max

NOTES

1Measured using internal RFB A and RFB B.

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

REV. B

–5–