White Electronic Designs WMS256K16L-35FLMA, WMS256K16L-35FLIA, WMS256K16L-35FLCA, WMS256K16L-35FLC, WMS256K16L-35FGMA Datasheet

WMS256K16-XXX

HI-RELIABILITY PRODUCT

256Kx16 MONOLITHIC SRAM, SMD 5962-96902

FEATURES

■Access Times 17, 20, 25, 35ns

■MIL-STD-883 Compliant Devices Available

■Packaging

•44 pin Ceramic SOJ (Package 102)

•44 lead Ceramic Flatpack (Package 225)

•44 lead Formed Ceramic Flatpack

■Organized as 256Kx16

■Data Byte Control:

Lower Byte (LB) = I/O1-8

Upper Byte (UB) = I/O9-16

■2V Minimum Data Retention for battery back up operation (WMS256K16L-XXX Low Power Version Only)

■Commercial, Industrial and Military Temperature Range

■5 Volt Power Supply

■Low Power CMOS

■TTL Compatible Inputs and Outputs

PIN CONFIGURATION FOR WMS256K16-XXX

44 CSOJ

PIN DESCRIPTION

44 FLATPACK

A0-17

Address Inputs

TOP VIEW

LB

Lower-Byte Control (I/O1-8)

A0

1

44

A17

Upper-Byte Control (I/O9-16)

UB

A1

2

43

A16

I/O1-16

Data Input/Output

A2

3

42

A15

41

A3

4

Chip Select

OE

CS

A4

5

40

UB

OE

Output Enable

6

39

CS

LB

7

38

Write Enable

I/O1

I/O16

WE

I/O2

8

37

I/O15

VCC

+5.0V Power

I/O3

9

36

I/O14

I/O4

10

35

I/O13

GND

Ground

VCC

11

34

GND

NC

No Connection

GND

12

33

VCC

I/O5

13

32

I/O12

I/O6

14

31

I/O11

I/O7

15

30

I/O10

I/O8

16

29

I/O9

17

28

WE

NC

A5

18

27

A14

A6

19

26

A13

A7

20

25

A12

A8

21

24

A11

A9

22

23

A10

October 2000 Rev. 4

1

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WMS256K16-XXX

TRUTH TABLE

CS

WE

OE

LB

UB

Mode

Data I/O

Power

I/O1-8

I/O9-16

H

X

X

X

X

Not Select

High Z

High Z

Standby

L

H

H

X

X

Output Disable

High Z

High Z

Active

L

X

X

H

H

L

H

Data Out

High Z

L

H

L

H

L

Read

High Z

Data Out

Active

L

L

Data Out

Data Out

L

H

Data In

High Z

L

L

X

H

L

Write

High Z

Data In

Active

L

L

Data In

Data In

ABSOLUTE MAXIMUM RATINGS

Parameter	Symbol	Min	Max	Unit
Operating Temperature	TA	-55	+125	°C
Storage Temperature	TSTG	-65	+150	°C
Signal Voltage Relative to GND	VG	-0.5	Vcc+0.5	V
Junction Temperature	TJ		150	°C
Supply Voltage	VCC	-0.5	7.0	V

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Max	Unit
Supply Voltage	VCC	4.5	5.5	V
Input High Voltage	VIH	2.2	VCC + 0.3	V
Input Low Voltage	VIL	-0.3	+0.8	V
Operating Temp. (Mil.)	TA	-55	+125	°C

CAPACITANCE

(TA = +25°C)

Parameter	Symbol	Condition	Max	Unit
Input capacitance	CIN	VIN = 0V, f = 1.0MHz	20	pF
Output capicitance	COUT	VOUT = 0V, f = 1.0MHz	20	pF

This parameter is guaranteed by design but not tested.

DC CHARACTERISTICS

(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)

Parameter

Sym

Conditions

Min

Max

Units

Input Leakage Current

ILI

VCC = 5.5, VIN = GND to VCC

10

A

Output Leakage Current

ILO

= VIH,

= VIH, VOUT = GND to VCC

10

A

CS

OE

Operating Supply Current

ICC

= VIL,

= VIH, f = 5MHz, Vcc = 5.5

275

mA

CS

OE

Standby Current

ISB

= VIH,

= VIH, f = 5MHz, Vcc = 5.5

17

mA

CS

OE

Output Low Voltage

VOL

IOL = 8mA, VCC = 4.5

0.4

V

Output High Voltage

VOH

IOH = -4.0mA, VCC = 4.5

2.4

V

NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V

LOW POWER DATA RETENTION CHARACTERISTICS (WMS256K16L-XXX ONLY)

(TA = -55°C to +125°C)

Parameter	Symbol		Conditions					Units
					Min	Typ	Max
Data Retention Supply Voltage	VDR		CS	≥ VCC -0.2V	2.0		5.5	V
Data Retention Current	ICCDR1			VCC = 3V		1.0	8.0	mA

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2

WMS256K16-XXX

AC CHARACTERISTICS

(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)

	Parameter										Symbol		-17			-20			-25			-35		Units
	Read Cycle											Min		Max	Min		Max	Min		Max	Min		Max
	Read Cycle Time										tRC	17			20			25			35			ns
	Address Access Time										tAA			17			20			25			35	ns
	Output Hold from Address Change										tOH	0			0			0			0			ns
	Chip Select Access Time										tACS			17			20			25			35	ns
	Output Enable to Output Valid										tOE			10			12			15			20	ns
	Chip Select to Output in Low Z										tCLZ1	2			5			5			5			ns
	Output Enable to Output in Low Z										tOLZ1	0			0			0			0			ns
	Chip Disable to Output in High Z										tCHZ1			9			10			12			15	ns
	Output Disable to Output in High Z										tOHZ1			9			10			12			15	ns
											tBA			10			12			14			17	ns
	LB,							UB		Access Time
											tBLZ1	0			0			0			0			ns
		LB,					UB		Enable to Low Z Output
											tBHZ1			9			10			12			15	ns
			LB,				UB			Disable to High Z Output

1. This parameter is guaranteed by design but not tested.

AC CHARACTERISTICS

(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)

	Parameter				Symbol	-17				-20			-25			-35		Units
	Write Cycle					Min		Max	Min		Max	Min		Max	Min		Max
	Write Cycle Time				tWC	17			20			25			35			ns
	Chip Select to End of Write				tCW	14			17			20			25			ns
	Address Valid to End of Write				tAW	14			17			20			25			ns
	Data Valid to End of Write				tDW	10			12			15			20			ns
	Write Pulse Width				tWP	14			17			20			25			ns
	Address Setup Time				tAS	0			0			0			0			ns
	Address Hold Time				tAH	2			2			2			2			ns
	Output Active from End of Write				tOW1	0			0			0			0			ns
	Write Enable to Output in High Z				tWHZ1			9			10			10			15	ns
	Data Hold Time				tDH	0			0			0			0			ns
					tBW	14			17			20			25			ns
	LB,		UB	Valid to End of Write

1. This parameter is guaranteed by design but not tested.

AC TEST CIRCUIT

	I OL
	Current Source
D.U.T.	VZ ≈1.5V
Ceff = 50 pf	(Bipolar Supply)

IOH

Current Source

AC TEST CONDITIONS

Parameter	Typ	Unit
Input Pulse Levels	VIL = 0, VIH = 3.0	V
Input Rise and Fall	5	ns
Input and Output Reference Level	1.5	V
Output Timing Reference Level	1.5	V

NOTES:

VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω.

VZ is typically the midpoint of VOH and VOL.

IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.

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