White Electronic Designs WF2M16W-90FLM5A, WF2M16W-90FLM5, WF2M16W-90FLI5A, WF2M16W-90FLI5, WF2M16W-90FLC5A Datasheet

WF2M16-XXX5

2Mx16 FLASH MODULE, SMD 5962-97610 (pending)

FEATURES

HI-RELIABILITY PRODUCT

PRELIMINARY*

■Access Times of 90, 120, 150ns

■Packaging:

•56 lead, Hermetic Ceramic, 0.520" CSOP (Package 207). Fits standard 56 SSOP footprint.

•44 pin Ceramic SOJ (Package 102)**

•44 lead Ceramic Flatpack (Package 208)**

■Sector Architecture

•32 equal size sectors of 64KBytes each

•Any combination of sectors can be erased. Also supports full chip erase.

■Minimum 100,000 Write/Erase Cycles Minimum

■Organized as 2Mx16; User Configurable as 2 x 2Mx8

■Commercial, Industrial, and Military Temperature Ranges

■5 Volt Read and Write. 5V ± 10% Supply.

■Low Power CMOS

■Data Polling and Toggle Bit feature for detection of program or erase cycle completion.

■Supports reading or programming data to a sector not being erased.

■Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation.

■RESET pin resets internal state machine to the read mode.

■Ready/Busy (RY/BY) output for detection of program or erase cycle completion.

■Multiple Ground Pins for Low Noise Operation

*This data sheet describes a product under development, not fully characterized, and is subject to change without notice.

* * Package to be developed.

Note: For programming information refer to Flash Programming 16M5 Application Notes.

FIG. 1 PIN CONFIGURATIONS

WF2M16-XDAX5

56 CSOP

TOP VIEW

									1	56
CS1											NC
	A12								2	55		RESET
	A13								3	54	A11
	A14								4	53	A10
	A15								5	52	A9
			NC						6	51	A1
									7	50
	CS2										A2
			NC						8	49	A3
	A20								9	48	A4
	A19								10	47	A5
	A18								11	46	A6
	A17								12	45	A7
	A16								13	44	GND
		VCC							14	43	A8
GND									15	42	VCC
I/O6									16	41	I/O9
I/O14									17	40	I/O1
I/O7									18	39	I/O8
I/O15									19	38	I/O0
									20	37	A0
RY/BY
			OE						21	36	NC
		WE							22	35	NC
			NC						23	34	NC
I/O13									24	33	I/O2
I/O5									25	32	I/O10
I/O12									26	31	I/O3
I/O4									27	30	I/O11
		VCC							28	29	GND

WF2M16-XXX5

44 CSOJ (DL)**

44 FLATPACK (FL)**

TOP VIEW

		A15						1	44			A16
		A14						2	43			A17
		A13						3	42			A18
		A12						4	41			A19
		A11						5	40			A20
		A10						6	39
													OE
			A9					7	38			I/O7
			A8					8	37			I/O6
								9	36			I/O5
	RESET
								10	35			I/O4
		CS1
		VCC						11	34			VSS
		VSS						12	33			VCC
								13	32			I/O3
		CS2
								14	31
	RY/BY											I/O2
			A7					15	30			I/O1
			A6					16	29			I/O0
			A5					17	28
												WE
			A4					18	27			NC
			A3					19	26			NC
			A2					20	25			NC
			A1					21	24			NC
			A0					22	23			NC

** Package to be developed.

PIN DESCRIPTION

	I/O0-15										Data Inputs/Outputs
		A0-20									Address Inputs
											Write Enable
			WE
					1-2						Chip Select
		CS
											Output Enable
				OE
		VCC									Power Supply
		VSS									Ground
											Ready/Busy
	RY/BY
											Reset
	RESET

BLOCK DIAGRAM

I/O 0 - 7 I/O 8 - 1 5

RESET

WE

OE

A 0 - 2 0

RY/BY

2M x 8		2M x 8

CS 1

CS 2

NOTE:

1. RY/BY is an open drain output and should be pulled up to Vcc with an external resistor.

2. Address compatible with Intel 2M8 56 SSOP.

November 1999 Rev. 3

1

White Electronic Designs Corporation • [phone] • www.whiteedc.com

WF2M16-XXX5

ABSOLUTE MAXIMUM RATINGS

Parameter	Symbol	Ratings	Unit
Voltage on Any Pin Relative to VSS	VT	-2.0 to +7.0	V
Power Dissipation	PT	8	W
Storage Temperature	Tstg	-65 to +125	°C
Short Circuit Output Current	IOS	100	mA
Data Retention (Mil Temp)		20	years
Endurance - write/erase cycles		100,000 min.	cycles
(Mil Temp)

CAPACITANCE

(TA = +25°C)

	Parameter					Symbol	Conditions	Max	Unit
					capacitance	COE	VIN = 0 V, f = 1.0 MHz	25	pF
	OE
					capacitance	CWE	VIN = 0 V, f = 1.0 MHz	25	pF
	WE
			capacitance			CCS	VIN = 0 V, f = 1.0 MHz	15	pF
		CS
	Data I/O capacitance					CI/O	VI/O = 0 V, f = 1.0 MHz	15	pF
	Address input capacitance					CAD	VIN = 0 V, f = 1.0 MHz	25	pF

This parameter is guaranteed by design but not tested.

RECOMMENDED DC OPERATING CONDITIONS

Parameter	Symbol	Min	Typ	Max	Unit
Supply Voltage	VCC	4.5	5.0	5.5	V
Ground	VSS	0	0	0	V
Input High Voltage	VIH	2.0	-	VCC + 0.5	V
Input Low Voltage	VIL	-0.5	-	+0.8	V
Operating Temperature (Mil.)	TA	-55	-	+125	°C
Operating Temperature (Ind.)	TA	-40	-	+85	°C

DC CHARACTERISTICS - CMOS COMPATIBLE

(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)

Parameter

Symbol

Conditions

Min

Max

Unit

Input Leakage Current

ILI

VCC = 5.5, VIN = GND to VCC

10

A

Output Leakage Current

ILO

VCC = 5.5, VIN = GND to VCC

10

A

VCC Active Current for Read (1)

ICC1

= VIL,

= VIH, f = 5MHz

80

mA

CS

OE

VCC Active Current for Program or Erase (2)

ICC2

= VIL,

= VIH

120

mA

CS

OE

VCC Standby Current

ICC3

VCC = 5.5,

= VIH, f = 5MHz,

= Vcc ± 0.3V

4.0

mA

RESET

CS

Output Low Voltage

VOL

IOL = 12.0 mA, VCC = 4.5

0.45

V

Output High Voltage

VOH

IOH = -2.5 mA, VCC = 4.5

0.85xVcc

V

Low VCC Lock-Out Voltage

VLKO

3.2

4.2

V

NOTES:

1.The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than 2mA/MHz, with OE at VIH.

2.Icc active while Embedded Algorithm (program or erase) is in progress.

3.DC test conditions VIL = 0.3V, VIH = VCC - 0.3V

White Electronic Designs Corporation • [phone] • www.whiteedc.com

2

WF2M16-XXX5

AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED

(VCC = 5.0V, TA = -55°C to +125°C)

Parameter			Symbol		-90				-120			-150		Unit
					Min		Max	Min		Max	Min		Max
Write Cycle Time			tAVAV	tWC	90			120			150			ns
Chip Select Setup Time			tELWL	tCS	0			0			0			ns
Write Enable Pulse Width			tWLWH	tWP	45			50			50			ns
Address Setup Time			tAVWL	tAS	0			0			0			ns
Data Setup Time			tDVWH	tDS	45			50			50			ns
Data Hold Time			tWHDX	tDH	0			0			0			ns
Address Hold Time			tWLAX	tAH	45			50			50			ns
Write Enable Pulse Width High			tWHWL	tWPH	20			20			20			ns
Duration of Byte Programming Operation (1)			tWHWH1				300			300			300	s
Sector Erase (2)			tWHWH2				15			15			15	sec
Read Recovery Time before Write			tGHWL		0			0			0			s
VCC Setup Time			tVCS		50			50			50			s
Chip Programming Time							44			44			44	sec
Chip Erase Time (3)							256			256			256	sec
Output Enable Hold Time (4)				tOEH	10			10			10			ns
		Pulse Width		tRP	500			500			500			ns
	RESET

NOTES:

1.Typical value for tWHWH1 is 7 s.

2.Typical value for tWHWH2 is 1sec.

3.Typical value for Chip Erase Time is 32sec.

4.For Toggle and Data Polling.

AC CHARACTERISTICS – READ-ONLY OPERATIONS

(VCC = 5.0V, TA = -55°C to +125°C)

Parameter

Symbol

-90

-120

-150

Unit

Min

Max

Min

Max

Min

Max

Read Cycle Time

tAVAV

tRC

90

120

150

ns

Address Access Time

tAVQV

tACC

90

120

150

ns

Chip Select Access Time

tELQV

tCE

90

120

150

ns

Output Enable to Output Valid

tGLQV

tOE

40

50

55

ns

Chip Select High to Output High Z (1)

tEHQZ

tDF

20

30

35

ns

Output Enable High to Output High Z (1)

tGHQZ

tDF

20

30

35

ns

tOH

0

0

0

ns

Output Hold from Addresses,

CS

or

OE

Change,

tAXQX

whichever is First

Low to Read Mode (1)

tReady

20

20

20

s

RESET

1. Guaranteed by design, not tested.

3	White Electronic Designs Corporation • [phone] • www.whiteedc.com

WF2M16-XXX5

AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED

(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)

Parameter	Symbol			-90				-120			-150		Unit
				Min		Max	Min		Max	Min		Max
Write Cycle Time	tAVAV		tWC	90			120			150			ns
Write Enable Setup Time	tWLEL		tWS	0			0			0			ns
Chip Select Pulse Width	tELEH		tCP	45			50			50			ns
Address Setup Time	tAVEL		tAS	0			0			0			ns
Data Setup Time	tDVEH		tDS	45			50			50			ns
Data Hold Time	tEHDX		tDH	0			0			0			ns
Address Hold Time	tELAX		tAH	45			50			50			ns
Chip Select Pulse Width High	tEHEL		tCPH	20			20			20			ns
Duration of Byte Programming Operation (1)	tWHWH1					300			300			300	µs
Sector Erase Time (2)	tWHWH2					15			15			15	sec
Read Recovery Time	tGHEL			0			0			0			µs
Chip Programming Time						44			44			44	sec
Chip Erase Time (3)						256			256			256	sec
Output Enable Hold Time (4)			tOEH	10			10			10			ns

NOTES:

1.Typical value for tWHWH1 is 7µs.

2.Typical value for tWHWH2 is 1sec.

3.Typical value for Chip Erase Time is 32sec.

4.For Toggle and Data Polling.

FIG. 2
AC TEST CIRCUIT	I OL
Current Source

D.U.T.

Ceff = 50 pf

CS

IOH

Current Source

AC TEST CONDITIONS

	Parameter	Typ	Unit
	Input Pulse Levels	VIL = 0, VIH = 3.0	V
	Input Rise and Fall	5	ns
	Input and Output Reference Level	1.5	V
VZ ≈1.5V	Output Timing Reference Level	1.5	V

(Bipolar Supply)

NOTES:

VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω.

VZ is typically the midpoint of VOH and VOL.

The risingIOL & edgeIOH areofadjustedthe lastto simulateWE signaltypical resistive load circuit. ATE tester includes jig capacitance.

WE

Entire programming

or erase operations

FIG. 3

RY/BY

RESET TIMING DIAGRAM

tBUSY

RESET

tRP

tReady

White Electronic Designs Corporation • [phone] • www.whiteedc.com

4