8Mx32 5V FLASH MODULE ADVANCED*
FEATURES
■Access Time of 100, 120, 150ns
■Packaging:
•68 Lead, 40 mm (1.560") square hermetic CQFP, 5.2 mm (0.205") high (Package 503)
■Sector Architecture
•32 equal size sectors of 64KBytes per each 2Mx8 chip
•Any combination of sectors can be erased. Also supports full chip erase.
■100,000 Write/Erase Cycles Minimum
■Organized as 8Mx32
■Commercial, Industrial, and Military Temperature Ranges
■5 Volt Read and Write. 5V ± 10% Supply.
■Low Power CMOS
WF8M32-XG4DX5
HI-RELIABILITY PRODUCT
■Data Polling and Toggle Bit feature for detection of program or erase cycle completion.
■Supports reading or programming data to a sector not being erased.
■RESET pin resets internal state machine to the read mode. (Not available in HIP package for WF2M32-XHX5)
■Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation, Seperate Power and Ground Planes to improve noise immunity.
■Built in Buffering.
*This data sheet describes a product that may or may not be under development, and is subject to change or cancellation without notice.
Note: For programming information refer to Flash Programming 16M5 Application Note.
FIG. 1 PIN CONFIGURATION FOR WF8M32-XG4DX5
TOP VIEW |
PIN DESCRIPTION |
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NC |
A0 |
A1 |
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A2 |
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A3 |
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A4 |
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A5 |
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CS1 |
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GND |
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CS3 |
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WE A6 A7 A8 A9 A10 |
VCC |
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1 |
68 67 66 65 64 63 62 61 |
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I/O0 |
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60 |
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I/O16 |
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I/O1 |
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59 |
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I/O17 |
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I/O2 |
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I/O18 |
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I/O3 |
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I/O19 |
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I/O4 |
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I/O20 |
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I/O5 |
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55 |
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I/O21 |
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I/O6 |
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54 |
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I/O22 |
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I/O7 |
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I/O23 |
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GND |
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GND |
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I/O8 |
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I/O24 |
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I/O9 |
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50 |
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I/O25 |
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I/O10 |
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49 |
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I/O26 |
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1 |
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I/O11 |
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48 |
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I/O27 |
RESET |
4 |
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I/O12 |
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I/O28 |
CS 1-4 |
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1 |
I/O13 |
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I/O29 |
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WE |
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1 |
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OE |
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I/O14 |
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I/O30 |
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A0-22 |
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I/O15 |
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I/O31 |
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27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 |
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I/O0-31 |
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Data Inputs/Outputs |
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A0-22 |
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Address Inputs |
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WE |
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Write Enable |
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Chip Selects |
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CS |
1-4 |
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Output Enable |
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OE |
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VCC |
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Power Supply |
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Reset |
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RESET |
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GND |
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Ground |
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BLOCK DIAGRAM |
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NC |
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Not Connected |
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Interface |
1 |
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4 |
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23 |
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CS |
1 |
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CS |
2 |
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CS |
3 |
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CS |
4 |
VCC |
A11 |
A12 |
A13 |
A14 |
A15 |
A16 |
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CS2 |
OE |
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CS4 |
A17 |
A18 |
A19 |
A20 |
A21 |
RESET |
A22 |
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2M x 8 |
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2M x 8 |
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2M x 8 |
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2M x 8 |
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2M x 8 |
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2M x 8 |
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2M x 8 |
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2M x 8 |
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2M x 8 |
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2M x 8 |
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2M x 8 |
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2M x 8 |
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2M x 8 |
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2M x 8 |
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2M x 8 |
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2M x 8 |
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I/O 0 - 7 |
I/O 8 - 1 5 |
I/O 1 6 - 2 3 |
I/O 2 4 - 3 1 |
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8 |
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8 |
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32
I/O0-31
CS1 selects I/O0-7, CS2 selects I/O8-15, CS3 selects I/O16-23, CS4 selects I/O24-31
October 1999 Rev. 3 |
1 |
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com |
WF8M32-XG4DX5
ABSOLUTE MAXIMUM RATINGS
Parameter |
Symbol |
Ratings |
Unit |
Voltage on Any Pin Relative to VSS |
VT |
-2.0 to +7.0 |
V |
Power Dissipation |
PT |
8 |
W |
Storage Temperature |
Tstg |
-65 to +125 |
°C |
Short Circuit Output Current |
IOS |
100 |
mA |
Endurance - Write/Erase Cycles |
|
100,000 min |
cycles |
(Mil Temp) |
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|
Data Retention (Mil Temp) |
|
20 |
years |
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|
RECOMMENDED DC OPERATING CONDITIONS
Parameter |
Symbol |
Min |
Typ |
Max |
Unit |
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Supply Voltage |
VCC |
4.5 |
5.0 |
5.5 |
V |
Ground |
VSS |
0 |
0 |
0 |
V |
Input High Voltage |
VIH |
2.0 |
- |
VCC + 0.5 |
V |
Input Low Voltage |
VIL |
-0.5 |
- |
+0.8 |
V |
Operating Temperature (Mil.) |
TA |
-55 |
- |
+125 |
°C |
Operating Temperature (Ind.) |
TA |
-40 |
- |
+85 |
°C |
CAPACITANCE
(TA = +25°C)
|
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Parameter |
Symbol |
Conditions |
Max |
Unit |
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capacitance |
COE |
VIN = 0 V, f = 1.0 MHz |
20 |
pF |
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OE |
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CWE |
VIN = 0 V, f = 1.0 MHz |
20 |
pF |
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WE |
capacitance |
|||||||
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CCS |
VIN = 0 V, f = 1.0 MHz |
20 |
pF |
||||
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CS |
1-4 capacitance |
|||||||
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Data I/O capacitance |
CI/O |
VI/O = 0 V, f = 1.0 MHz |
60 |
pF |
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Address input capacitance |
CAD |
VIN = 0 V, f = 1.0 MHz |
20 |
pF |
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VIN = O V, f = 1.0 MHz |
20 |
pF |
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RESET capacitance |
CRST |
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This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS - CMOS COMPATIBLE
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter |
Symbol |
|
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Conditions |
Min |
Max |
Unit |
||
Input Leakage Current |
ILI |
VCC = 5.5, VIN = GND to VCC |
|
10 |
A |
||||||||||||
Output Leakage Current |
ILOx32 |
VCC = 5.5, VIN = GND to VCC |
|
10 |
A |
||||||||||||
VCC Active Current for Read (1) |
ICC1 |
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= VIH, f = 5MHz |
|
640 |
mA |
|||||||
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CS |
= VIL, |
OE |
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VCC Active Current for Program or Erase (2) |
ICC2 |
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CS |
|
= VIL, OE = VIH |
|
960 |
mA |
||||||||
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= Vcc ± 0.3V |
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VCC Standby Current |
ICC3 |
VCC = 5.5, |
CS |
= VIH, f = 5MHz, |
RESET |
|
160 |
mA |
|||||||||
Output Low Voltage |
VOL |
IOL = 12.0 mA, VCC = 4.5 |
|
0.45 |
V |
||||||||||||
Output High Voltage |
VOH |
IOH = -2.5 mA, VCC = 4.5 |
0.85 x |
|
V |
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Vcc |
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Low VCC Lock-Out Voltage |
VLKO |
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3.2 |
4.2 |
V |
NOTES:
1.The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than 2mA/MHz, with OE at VIH.
2.Icc active while Embedded Algorithm (program or erase) is in progress.
3.DC test conditions VIL = 0.3V, VIH = VCC - 0.3V
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 |
2 |
WF8M32-XG4DX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED
(VCC = 5.0V, TA = -55°C to +125°C)
Parameter |
Symbol |
-100 |
|
|
-120 |
|
-150 |
Unit |
||||||
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Min |
Max |
Min |
|
Max |
Min |
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Max |
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Write Cycle Time |
tAVAV |
tWC |
100 |
|
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120 |
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150 |
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ns |
||
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Chip Select Setup Time |
tELWL |
tCS |
0 |
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0 |
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0 |
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ns |
||
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Write Enable Pulse Width |
tWLWH |
tWP |
50 |
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50 |
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50 |
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ns |
||
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Address Setup Time |
tAVWL |
tAS |
0 |
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0 |
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0 |
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ns |
||
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Data Setup Time |
tDVWH |
tDS |
50 |
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50 |
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50 |
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ns |
||
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Data Hold Time |
tWHDX |
tDH |
0 |
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0 |
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0 |
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ns |
||
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Address Hold Time |
tWLAX |
tAH |
50 |
|
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50 |
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50 |
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ns |
||
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Write Enable Pulse Width High |
tWHWL |
tWPH |
20 |
|
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20 |
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20 |
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ns |
||
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Duration of Byte Programming Operation (1) |
tWHWH1 |
|
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300 |
|
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300 |
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300 |
s |
||
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Sector Erase (2) |
tWHWH2 |
|
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15 |
|
|
15 |
|
|
15 |
sec |
||
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Read Recovery Time before Write |
tGHWL |
|
0 |
|
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0 |
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0 |
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|
s |
||
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VCC Setup Time |
tVCS |
|
50 |
|
|
50 |
|
|
50 |
|
|
s |
||
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Chip Programming Time |
|
|
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|
44 |
|
|
44 |
|
|
44 |
sec |
||
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Chip Erase Time (3) |
|
|
|
|
256 |
|
|
256 |
|
|
256 |
sec |
||
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Output Enable Hold Time (4) |
|
tOEH |
10 |
|
|
10 |
|
|
10 |
|
|
ns |
||
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Pulse Width |
|
tRP |
500 |
|
|
500 |
|
|
500 |
|
|
ns |
RESET |
|
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|||||||
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|
NOTES:
1.Typical value for tWHWH1 is 7 s.
2.Typical value for tWHWH2 is 1sec.
3.Typical value for Chip Erase Time is 32sec.
4.For Toggle and Data Polling.
AC CHARACTERISTICS – READ-ONLY OPERATIONS
(VCC = 5.0V, TA = -55°C to +125°C)
Parameter |
Symbol |
|
-100 |
|
-120 |
|
-150 |
Unit |
||||||||
|
|
|
|
|
|
|
Min |
|
Max |
Min |
|
Max |
Min |
|
Max |
|
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|
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|
Read Cycle Time |
tAVAV |
tRC |
100 |
|
|
120 |
|
|
150 |
|
|
ns |
||||
|
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|
|
Address Access Time |
tAVQV |
tACC |
|
|
100 |
|
|
120 |
|
|
150 |
ns |
||||
|
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|
|
Chip Select Access Time |
tELQV |
tCE |
|
|
100 |
|
|
120 |
|
|
150 |
ns |
||||
|
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|
Output Enable to Output Valid |
tGLQV |
tOE |
|
|
50 |
|
|
50 |
|
|
55 |
ns |
||||
|
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|
Chip Select High to Output High Z (1) |
tEHQZ |
tDF |
|
|
30 |
|
|
30 |
|
|
35 |
ns |
||||
|
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|
Output Enable High to Output High Z (1) |
tGHQZ |
tDF |
|
|
30 |
|
|
30 |
|
|
35 |
ns |
||||
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Output Hold from Addresses, |
|
or |
|
Change, |
tAXQX |
tOH |
0 |
|
|
0 |
|
|
0 |
|
|
ns |
CS |
OE |
|
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|||||||||
whichever is First |
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RST Low to Read Mode (1) |
|
tReady |
|
|
20 |
|
|
20 |
|
|
20 |
s |
1. Guaranteed by design, not tested.
3 |
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 |