White Electronic Designs WE32K32N-90G2UIA, WE32K32N-90G2UI, WE32K32N-90G2UCA, WE32K32N-90G2UC, WE32K32N-80H1QA Datasheet

WE32K32-XXX

HI-RELIABILITY PRODUCT

32Kx32 EEPROM MODULE, SMD 5962-94614

FEATURES

■Access Times of 80*, 90, 120, 150ns

■MIL-STD-883 Compliant Devices Available

■Packaging:

•68 lead, Hermetic CQFP (G2U), 22.4mm (0.880") square, 3.56mm (0.140") height (Package 510). Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 2)

•66-pin, PGA Type, 1.075" square, Hermetic Ceramic HIP (Package 400)

■Data Retention at 25°C, 10 Years

■Write Endurance, 10,000 Cycles

■Organized as 32Kx32; User Configurable 64Kx16 or 128Kx8

■Commercial, Industrial and Military Temperature Ranges

■Automatic Page Write Operation

■Page Write Cycle Time: 10ms Max

■Data Polling for End of Write Detection

■Hardware and Software Data Protection

■TTL Compatible Inputs and Outputs

■5 Volt Power Supply

■Low Power CMOS, 10mA Standby Typical

■Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation

*80ns speed is not fully characterized and is subject to change or cancellation without notice.

FIG. 1 PIN CONFIGURATION FOR WE32K32N-XH1X
		TOP VIEW							PIN DESCRIPTION
1	12	23		34	45	56			I/O0-31	Data Inputs/Outputs
I/O8	WE2	I/O15	I/O24		VCC	I/O31			A0-14	Address Inputs
I/O9	CS2	I/O14	I/O25		CS4	I/O30			WE1-4	Write Enables
I/O10	GND	I/O13	I/O26		WE4	I/O29			CS1-4	Chip Selects
A13	I/O11	I/O12	A6		I/O27	I/O28			OE	Output Enable
									VCC	Power Supply
A14	A10	OE	A7		A3	A0			GND	Ground
NC	A11	NC	NC		A4	A1			NC	Not Connected
NC	A12	WE1	A8		A5	A2		BLOCK DIAGRAM
NC	VCC	I/O7	A9		WE3	I/O23	WE1 CS1	WE2 CS2	WE3 CS3	WE4 CS 4
							OE
I/O0	CS1	I/O6	I/O16		CS3	I/O22	A 0 - 1 4
I/O1	NC	I/O5	I/O17		GND	I/O21	32K x 8	32K x 8	32K x 8	32K x 8
I/O2	I/O3	I/O4	I/O18		I/O19	I/O20
11	22	33		44	55	66	8	8	8	8
							I/O 0 - 7	I/O 8 - 1 5	I/O 1 6 - 2 3	I/O 2 4 - 3 1

June 1999 Rev. 2

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White Electronic Designs Corporation • Phoenix, AZ • [phone]

WE32K32-XXX

FIG. 2

PIN CONFIGURATION FOR WE32K32-XG2UX

TOP VIEW

PIN DESCRIPTION

NC

A0

A1

A2

A3

A4

A5

CS3

GND

CS4

WE1

A6

A7

A8

A9

A10

VCC

I/O0-31

Data Inputs/Outputs

9

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

A0-14

Address Inputs

1-4

Write Enables

I/O0

10

60

I/O16

WE

I/O1

11

59

I/O17

1-4

Chip Selects

CS

I/O2

12

58

I/O18

OE

Output Enable

I/O3

13

57

I/O19

VCC

Power Supply

I/O4

14

56

I/O20

GND

Ground

I/O5

15

55

I/O21

NC

Not Connected

I/O6

16

54

I/O22

I/O7

17

53

I/O23

GND

18

52

GND

I/O8

19

51

I/O24

I/O9

20

50

I/O25

I/O10

21

49

I/O26

I/O11

22

48

I/O27

I/O12

23

47

I/O28

I/O13

24

46

I/O29

I/O14

25

45

I/O30

I/O15

26

44

I/O31

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

VCC

A11

A12

A13

A14

NC

NC

CS1

OE

CS2 NC

WE2

WE3

WE4

NC

NC

NC

OE

A 0 - 1 4

							BLOCK DIAGRAM
											2		2						3		3					4			4
			WE	1	CS	1			WE			CS					WE			CS				WE			CS
																																						0.940"

	32K x 8		32K x 8		32K x 8		32K x 8	The White 68 lead G2U CQFP
								fills the same fit and function as
	8	8		8		8		the JEDEC 68 lead CQFJ or 68
								PLCC. But the G2U has the TCE
	I/O 0 - 7		I/O 8 - 1 5		I/O 1 6 - 2 3		I/O 2 4 - 3 1	and lead inspection advantage
								of the CQFP form.

White Electronic Designs Corporation • Phoenix, AZ • [phone]

2

WE32K32-XXX

ABSOLUTE MAXIMUM RATINGS

Parameter			Symbol		Unit
Operating Temperature			TA	-55 to +125	°C
Storage Temperature			TSTG	-65 to +150	°C
Signal Voltage Relative to GND			VG	-0.6 to +6.25	V
Voltage on		and A9		-0.6 to +13.5	V
	OE

NOTE:

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min		Max	Unit
Supply Voltage	VCC	4.5		5.5	V
Input High Voltage	VIH	2.0		VCC + 0.3	V
Input Low Voltage	VIL	-0.5		+0.8	V
Operating Temp. (Mil.)	TA	-55		+125	°C
Operating Temp. (Ind.)	TA	-40		+85	°C

TRUTH TABLE

	CS			OE			WE		Mode		Data I/O
	H			X			X		Standby		High Z
	L			L			H		Read		Data Out
	L			H			L		Write		Data In
	X			H			X		Out Disable		High Z/Data Out
	X			X			H		Write
	X			L			X		Inhibit

CAPACITANCE

(TA = 25° C)

	Parameter			Symbol	Condition	Max	Unit
	Address Input Capacitance			CAD	VIN = 0V, f = 1.0MHz	50	pF
	OE Capacitance			COE
		1-4 Capacitance		CCS	VIN = 0V, f = 1.0MHz	20	pF
	CS
			1-4 Capacitance	CWE	VIN = 0V, f = 1.0MHz	20	pF
	WE
	Data I/O Capacitance			CI/O	VIN = 0V, f = 1.0MHz	20	pF

This parameter is guaranteed by design but not tested.

DC CHARACTERISTICS

(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)

Parameter	Symbol										Conditions		-80		-90		-120		-150		Units
												Min		Max	Min Max		Min Max		Min Max
Input Leakage Current	ILI	VCC = 5.5, VIN = GND to VCC												10		10		10		10	µA
Output Leakage Current	ILO x 32					= VIH,					= VIH, VOUT = GND to VCC			10		10		10		10	µA
			CS					OE
Operating Supply Current x 32 Mode	ICC x 32					= VIL,					= VIH, f = 5MHz			320		250		200		150	mA
			CS				OE
Standby Current	ISB					= VIH,					= VIH, f = 5MHz			2.5		2.5		2.5		2.5	mA
				CS				OE
Output Low Voltage	VOL	IOL = 2.1mA, VCC = 4.5V												0.45		0.45		0.45		0.45	V
Output High Voltage	VOH	IOH = -400µA, VCC = 4.5V										2.4			2.4		2.4		2.4		V

NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V

FIG. 3

AC TEST CIRCUIT

I OL

Current Source

D.U.T.	VZ ≈1.5V
Ceff = 50 pf	(Bipolar Supply)

IOH

Current Source

AC TEST CONDITIONS

Parameter	Typ	Unit
Input Pulse Levels	VIL = 0, VIH = 3.0	V
Input Rise and Fall	5	ns
Input and Output Reference Level	1.5	V
Output Timing Reference Level	1.5	V

NOTES:

VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω.

VZ is typically the midpoint of VOH and VOL.

IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.

3	White Electronic Designs Corporation • Phoenix, AZ • [phone]

WE32K32-XXX

WRITE

A write cycle is initiated when OE is high and a low pulse is on WE or CS with CS or WE low. The address is latched on the falling edge of CS or WE whichever occurs last. The data is latched by the rising edge of CS or WE, whichever occurs first. A byte write operation will automatically continue to completion.

WRITE CYCLE TIMING

Figures 4 and 5 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the CS line low. Write enable consists of setting the WE line low. The write cycle begins when the last of either CS or WE goes low.

The WE line transition from high to low also initiates an internal 150 sec delay timer to permit page mode operation. Each subsequent WE transition from high to low that occurs before the completion of the 150 sec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot.

AC WRITE CHARACTERISTICS

(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)

WRITE CYCLE							-80			-90			-120			-150
Write Cycle Parameter					Symbol	Min		Max	Min		Max	Min		Max	Min		Max	Unit
Write Cycle Time, TYP = 6ms					tWC			10			10			10			10	ms
Address Set-up Time					tAS	0			0			30			30			ns
Write Pulse Width		or			tWP	100			100			150			150			ns
	(WE		CS)
Chip Select Set-up Time					tCS	0			0			0			0			ns
Address Hold Time					tAH	50			50			100			100			ns
Data Hold Time					tDH	0			0			10			10			ns
Chip Select Hold Time					tCSH	0			0			0			0			ns
Data Set-up Time					tDS	50			50			100			100			ns
Write Pulse Width High					tWPH	50			50			50			50			ns
Output Enable Set-up Time					tOES	10			10			10			10			ns
Output Enable Hold Time					tOEH	10			10			10			10			ns

White Electronic Designs Corporation • Phoenix, AZ • [phone]

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