White Electronic Designs WF4M32-150G4TM5A, WF4M32-150G4TM5, WF4M32-150G4TI5A, WF4M32-150G4TI5, WF4M32-150G4TC5A Datasheet

...

0 (0)

White Electronic Designs

WF4M32-XXX5

4MX32 5V FLASH MODULE, SMD 5962-97612 (pending) PRELIMINARY*

FEATURES

νAccess Times of 100, 120, 150ns

νPackaging:

•66 pin, PGA Type, 1.385" square, Hermetic Ceramic HIP (Package 402).

•68 lead, 40mm Low Profile CQFP ( Package

502 ), 3.5mm (0.140") height.

•68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square (Package 509) 4.57mm (0.180") height. Designed to fit JEDEC 68 lead 0.990CQFJ footprint (Fig. 3)

νSector Architecture

•32 equal size sectors of 64KBytes per each 2Mx8 chip

•Any combination of sectors can be erased. Also supports full chip erase.

νMinimum 100,000 Write/Erase Cycles Minimum

νOrganized as 4Mx32

νUser configurable as 8Mx16 or 16Mx8 in HIP and G4T packages.

νCommercial, Industrial, and Military Temperature Ranges

ν5 Volt Read and Write. 5V ± 10% Supply.

νLow Power CMOS

νData Polling and Toggle Bit feature for detection of program or erase cycle completion.

νSupports reading or programming data to a sector not being erased.

νRESET pin resets internal state machine to the read mode.

νBuilt-in Decoupling Caps and Multiple Ground

Pins for Low Noise Operation, Separate Power and Ground Planes to improve noise immunity

*This data sheet describes a product under development, not fully characterized, and is subject to change without notice.

Note:

For programming information refer to Flash Programming 16M5 Application Note.

FIG. 1	PIN CONFIGURATION FOR WF4M32-XH2X5							PIN DESCRIPTION
		TOP VIEW						I/O0-31 DataInputs/Outputs
1	12	23		34	45	56		A0-21	AddressInputs
								A0-21	AddressInputs
I/O8	RESET	I/O15	I/O24		VCC	I/O31		WE	Write Enables
I/O9	CS2	I/O14	I/O25		CS4	I/O30		CS1-4	Chip Selects
I/O9	CS2	I/O14	I/O25		CS4	I/O30		OE	OutputEnable
								OE	OutputEnable
I/O10	GND	I/O13	I/O26		NC	I/O29		VCC	Power Supply
								VCC	Power Supply
A14	I/O11	I/O12	A7		I/O27	I/O28		GND	Ground
								RESET	Reset
A16	A10	OE	A12		A4	A1
A11	A9	A17	A21		A5	A2		BLOCK DIAGRAM
								BLOCK DIAGRAM
A0	A15	WE	A13		A6	A3	CS1	CS2	CS3		CS4
							A21
A18	VCC	I/O7	A8		A20	I/O23
I/O0	CS1	I/O6	I/O16		CS3	I/O22
							OE
							WE
I/O1	A19	I/O5	I/O17		GND	I/O21	A0-20
							RESET
I/O2	I/O3	I/O4	I/O18		I/O19	I/O20	2M x 8	2M x 8	2Mx 8		2M x 8
I/O2	I/O3	I/O4	I/O18		I/O19	I/O20
11	22	33		44	55	66		2M x 8	2M x 8	2M x 8	2M x 8
11	22	33		44	55	66
								I/O0-7	I/O8-15	I/O16-23	I/O24-31

August 2002 Rev. 4

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

WF4M32-XXX5

FIG. 2

PIN CONFIGURATION FOR WF4M32-XG4TX5

PIN DESCRIPTION

TOP VIEW

I/O0-31

Data

Inputs/Outputs

NC A0

CS1

GND

CS3

WE A6

A10

VCC

A0-21

AddressInputs

Write Enable

CS1-4

Chip Selects

68 67 66 65 64 63 62 61

OutputEnable

I/O0

I/O16

VCC

PowerSupply

I/O1

I/O17

Reset

I/O2

I/O18

RESET

I/O3

I/O19

GND

Ground

I/O4

I/O20

I/O5

I/O21

Not Connected

I/O6

I/O22

I/O7

I/O23

BLOCK DIAGRAM

GND

I/O8

I/O24

I/O9

I/O25

CS1

CS2

CS3

CS4

A21

I/O10

I/O26

I/O11

I/O27

I/O12

I/O28

I/O13

I/O29

I/O14

I/O30

I/O15

I/O31

BUFFER

A0-20

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

RESET

VCC A11 A12 A13 A14 A15 A16

CS2

CS4 A17 A18 A19 A20 A21

RESET NC

2M x 8

I/O0-7

I/O8-15

I/O16-23

I/O24-31

FIG. 3 PIN CONFIGURATION FOR WF4M32-XG2TX5

TOP VIEW

		RESET	A0	A1	A2	A3	A4	A5	NC	GND	NC	WE	A6	A7	A8	A9	A10	VCC


	9		8	7	6	5	4	3	2	1	68 67 66 65 64 63 62 61
I/O0	10																	60	I/O16
I/O1	11																	59	I/O17
I/O2	12																	58	I/O18
I/O3	13																	57	I/O19
I/O4	14																	56	I/O20
I/O5	15																	55	I/O21
I/O6	16																	54	I/O22
I/O7	17																	53	I/O23
GND	18																	52	GND
I/O8	19																	51	I/O24

The White 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form.

I/O9 20

50 I/O25

PIN DESCRIPTION

I/O0-31				DataInputs/Outputs
A0-20				AddressInputs


		WE		Write Enables


	CS1-2			Banks Selects

				OutputEnable
			OE	OutputEnable

		VCC		Power Supply

	GND			Ground

				Reset
RESET				Reset

BLOCK DIAGRAM

I/O10

I/O26

I/O11

I/O27

I/O12

I/O28

I/O13

I/O29

I/O14

I/O30

I/O15

I/O31

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

VCC

A11

A12 A13 A14 A15 A16

CS1

CS2 A17 NC NC NC

A18

A19

A20

CS1

RESET

A0-20

2M x 8

CS2

I/O8-15

I/O16-23

I/O24-31

I/O0-7

Note: CS1& CS2 are used as bank select

White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520

White Electronic Designs

WF4M32-XXX5

ABSOLUTE MAXIMUM RATINGS

Parameter		Symbol		Ratings			Unit
Voltage on Any Pin Relative to VSS			VT	-2.0 to +7.0			V
Power Dissipation			PT		8		W
Storage Temperature			Tstg	-65 to +125			°C
ShortCircuitOutputCurrent			IOS		100		mA
Endurance - Write/Erase Cycles				100,000 min			cycles
(Mil Temp)
Data Retention (Mil Temp)					20		years

RECOMMENDED DC OPERATING CONDITIONS

Parameter	Symbol		Min	Typ		Max	Unit

Supply Voltage	VCC		4.5	5.0		5.5	V
Ground	VSS		0	0		0	V
Input High Voltage	VIH		2.0	-		VCC + 0.5	V
Input Low Voltage	VIL		-0.5	-		+0.8	V
Operating Temperature (Mil.)	TA		-55	-		+125	°C
Operating Temperature (Ind.)	TA		-40	-		+85	°C

CAPACITANCE (PF)

(TA = +25°C, VIN = OV, F = 1.0MHZ)

Parameter				Symbol	HIP (H2)	CQFP (G2T)	CQFP( G4T)
			capacitance	COE	75	75	20
OE			capacitance	COE	75	75	20

WE capacitance				CWE	75	75	20
		capacitance		CCS	20	50	20
	CS	capacitance		CCS	20	50	20
Data I/O capacitance				CI/O	30	30	30
Addressinputcapacitance				CAD	75	75	20

This parameter is guaranteed by design but not tested.

DC CHARACTERISTICS - CMOS COMPATIBLE

(VCC = 5.0V, GND = 0V, TA = -55°C TO +125°C)

Parameter

Symbol

Conditions

HIP

G2T

G4T

Unit

Min

Max

Min

Max

Min

Max

InputLeakageCurrent

ILI

VCC = 5.5, VIN = GND to VCC

µA

OutputLeakageCurrent

ILOx32

VCC = 5.5, VIN = GND to VCC

µA

VCC Active Current forRead (1)

ICC1

CS = VIL, OE = VIH, f = 5MHz

320

215

345

VCC ActiveCurrentforProgram

ICC2

= VIL,OE

VIH

420

295

445

orErase(2)

VCC StandbyCurrent

ICC3

2.0

VCC = 5.5, CS = VIH, f = 5MHz, RESET = VIH

OutputLowVoltage

VOL

IOL = 12.0 mA, VCC = 4.5

0.45

OutputHighVoltage

VOH

IOH = -2.5 mA, VCC = 4.5

0.85 x

Vcc

LowVCC Lock-OutVoltage

VLKO

3.2

4.2

3.2

4.2

3.2

4.2

NOTES:

1.The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than 2mA/MHz, with OE at VIH.

2.Icc active while Embedded Algorithm (program or erase) is in progress.

3.DC test conditions VIL = 0.3V, VIH = VCC - 0.3V

HIP = 66 pin, PGA Type, 1.385" square, Hermetic

Ceramic HIP (Package 402).

G2T = 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square. Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 3) (Package 509)

G4T = 68 lead, 40mm Low Profile CQFP, 3.5mm (0.140") (Package 502 )

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

	White Electronic Designs							WF4M32-XXX5

AC CHARACTERISTICS FOR G2T PACKAGE – WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED
		(VCC = 5.0V, TA = -55°C TO +125°C)

Parameter			Symbol		-100		-120		-150		Unit
					Min	Max	Min	Max	Min	Max
Write Cycle Time			tAVAV	tWC	100		120		150		ns

Chip Select Setup Time			tELWL	tCS	0		0		0		ns

Write Enable Pulse Width			tWLWH	tWP	45		50		50		ns

Address Setup Time			tAVWL	tAS	0		0		0		ns

Data Setup Time			tDVWH	tDS	45		50		50		ns

Data Hold Time			tWHDX	tDH	0		0		0		ns

Address Hold Time			tWLAX	tAH	45		50		50		ns

Write Enable Pulse Width High			tWHWL	tWPH	20		20		20		ns

Duration of Byte Programming Operation (1)			tWHWH1			300		300		300	µs

Sector Erase (2)			tWHWH2			15		15		15	sec

Read Recovery Time before Write			tGHWL		0		0		0		µs

VCC Setup Time			tVCS		50		50		50		µs

Chip Programming Time						44		44		44	sec

Chip Erase Time (3)						256		256		256	sec

Output Enable Hold Time (4)				tOEH	10		10		10		ns


RESET Pulse Width				tRP	500		500		500		ns

NOTES:

1.Typical value for tWHWH1 is 7µs.

2.Typical value for tWHWH2 is 1sec.

3.Typical value for Chip Erase Time is 32sec.

4.For Toggle and Data Polling.

AC CHARACTERISTICS FOR G2T PACKAGE – READ-ONLY OPERATIONS

(VCC = 5.0V, TA = -55°C TO +125°C)

Parameter

Symbol

-100

-120

-150

Unit

Min

Max

Min

Max

Min

Max

Read Cycle Time

tAVAV

tRC

100

120

150

Address Access Time

tAVQV

tA C C

100

120

150

Chip Select Access Time

tELQV

tCE

100

120

150

Output Enable to Output Valid

tGLQV

tOE

Chip Select High to Output High Z (1)

tEHQZ

tDF

Output Enable High to Output High Z (1)

tGHQZ

tDF

Output Hold from Addresses,

Change,

tAXQX

tOH

whichever is First

RST Low to Read Mode (1)

tReady

µs

1. Guaranteed by design, not tested.

White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520

White Electronic Designs						WF4M32-XXX5

AC CHARACTERISTICS FOR G2T PACKAGE – WRITE/ERASE/PROGRAM OPERATIONS							,CS		CONTROLLED
(VCC = 5.0V, GND = 0V, TA = -55°C TO +125°C)

Parameter	Symbol		-100		-120			-150			Unit
			Min	Max	Min	Max			Min	Max
Write Cycle Time	tAVAV	tWC	100		120			150			ns
Write Enable Setup Time	tWLEL	tWS	0		0			0			ns
Chip Select Pulse Width	tELEH	tCP	45		50			50			ns
Address Setup Time	tAVEL	tAS	0		0			0			ns
Data Setup Time	tDVEH	tDS	45		50			50			ns
Data Hold Time	tEHDX	tDH	0		0			0			ns
Address Hold Time	tELAX	tAH	45		50			50			ns
Chip Select Pulse Width High	tEHEL	tCPH	20		20			20			ns
Duration of Byte Programming Operation (1)	tWHWH1			300		300				300	µs
Sector Erase Time (2)	tWHWH2			15		15				15	sec
Read Recovery Time	tGHEL		0		0			0			µs
Chip Programming Time				44		44				44	sec
Chip Erase Time (3)				256		256				256	sec
Output Enable Hold Time (4)		tOEH	10		10			10			ns

NOTES:

1.Typical value for tWHWH1 is 7µs.

2.Typical value for tWHWH2 is 1sec.

3.Typical value for Chip Erase Time is 32sec.

4.For Toggle and Data Polling.

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

+ 10 hidden pages