White Electronic Designs WSF41632-22H2MA, WSF41632-22H2M, WSF41632-22H2IA, WSF41632-22H2CA, WSF41632-22H2I Datasheet

White Electronic Designs WSF41632-22XX

128KX32 SRAM & 512Kx32 FLASH MIXED MODULE PRELIMINARY*

FEATURES

■Access Times of 25ns (SRAM) and 120ns (FLASH)

■Packaging

•66 pin, PGA Type, 1.385" square HIP, Hermetic Ceramic HIP (Package 402)

•68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square (Package 509) 4.57mm (0.180") height. Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 2). Package to be developed.

■128Kx32 SRAM

■512Kx32 5V Flash

■Organized as 128Kx32 of SRAM and 512Kx32 of Flash Memory with common Data Bus

■Low Power CMOS

■Commercial,Industrial andMilitaryTemperatureRanges

■TTL Compatible Inputs and Outputs

■Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation

■Weight - 13 grams typical

FLASH MEMORY FEATURES

■100,000 Erase/Program Cycles Minimum

■Sector Architecture

•8 equal size sectors of 64KBytes each

•Any combination of sectors can be concurrently erased. Also supports full chip erase

■5 Volt Programming; 5V ± 10% Supply

■Embedded Erase and Program Algorithms

■Hardware Write Protection

■Page Program Operation and Internal Program Control Time.

*This data sheet describes a product under development, not fully characterized, and is subject to change without notice.

Note: For programming information refer to Flash Programming 4M5 Application Note.

FIG. 1	PIN CONFIGURATION FOR WSF41632-22H2X								PIN DESCRIPTION
		TOP VIEW							D0-31	Data Inputs/Outputs
1	12	23		34	45		56		A0-18	Address Inputs
I/O8	FWE2	I/O15	I/O24		VCC	I/O31			SWE1-4	SRAM Write Enables
									SCS	SRAM Chip Select
I/O9	SWE2	I/O14	I/O25		SWE4	I/O30			OE	Output Enable
I/O10	GND	I/O13	I/O26		FWE4	I/O29			VCC	Power Supply
A14	I/O11	I/O12	A7		I/O27	I/O28			GND		Ground
									NC	Not Connected
A16	A10	OE	A12		A4	A1			FWE1-4	Flash Write Enables
A11	A9	A17	SWE1		A5	A2			FCS	Flash Chip Select
A0	A15	FWE1	A13		A6	A3		BLOCK DIAGRAM
A18	VCC	I/O7	A8		FWE3	I/O23	FWE1 SWE1	FWE2 SWE2	FWE3	SWE3	FWE4 SWE4
							OE
I/O0	FCS	I/O6	I/O16		SWE3	I/O22	A0-18
							SCS
							FCS
I/O1	SCS	I/O5	I/O17		GND	I/O21	512K x 8 Flash	512K x 8 Flash	512K x 8 Flash		512K x 8 Flash
I/O2	I/O3	I/O4	I/O18		I/O19	I/O20	128K x 8 SRAM	128K x 8 SRAM	128K x 8 SRAM		128K x 8 SRAM
11	22	33		44	55		66
							I/O0-7	I/O8-15	I/O16-23		I/O24-31

October 2002 Rev. 4

1

White Electronic Designs Corporation • [phone] • www.whiteedc.com

White Electronic Designs		WSF41632-22XX
FIG. 2 PIN CONFIGURATION FOR WSF41632-22G2TX

TOP VIEW

	NC	A0	A1	A2	A3	A4	A5			SWE3		GND		SWE4		FWE1 A6 A7						A8	A9		A10		VCC
	9	8	7	6	5	4	3	2			1		68 67 66 65 64 63 62 61
I/O0	10																									60		I/O16
I/O1	11																									59		I/O17
I/O2	12																									58		I/O18
I/O3	13																									57		I/O19
I/O4	14																									56		I/O20
I/O5	15																									55		I/O21
I/O6	16																									54		I/O22
I/O7	17																									53		I/O23
GND	18																									52		GND
I/O8	19																									51		I/O24
I/O9	20																									50		I/O25
I/O10	21																									49		I/O26
I/O11	22																									48		I/O27
I/O12	23																									47		I/O28
I/O13	24																									46		I/O29
I/O14	25																									45		I/O30
I/O15	26																									44		I/O31
	27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
	VCC	A11	A12	A13	A14	A15	A16			FCS		OE		SWE2		NC		FWE2		FWE3		FWE4	NC		SCS		SWE1

0.940"

The WEDC 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form.

PIN DESCRIPTION

	D0-31								Data Inputs/Outputs
	A0-18								Address Inputs
SWE1-4									SRAM Write Enables
									SRAM Chip Select
		SCS
				OE					Output Enable
			VCC						Power Supply
	GND								Ground
				NC					Not Connected
									Flash Write Enables
	FWE				1-4
									Flash Chip Select
			FCS

BLOCK DIAGRAM

FWE1 SWE1

FWE2 SWE2

FWE3 SWE3

FWE4 SWE4

OE

A0-18

SCS

FCS

512K x 8 Flash

512K x 8 Flash

512K x 8 Flash

512K x 8 Flash

128K x

8 SRAM

128K x

8 SRAM

128K x

8 SRAM

128K x

8 SRAM

I/O0-7

I/O8-15

I/O16-23

I/O24-31

White Electronic Designs Corporation • Phoenix AZ • [phone]

2

White Electronic Designs

WSF41632-22XX

ABSOLUTE MAXIMUM RATINGS

Parameter	Symbol		Min		Max		Unit
Operating Temperature	TA		-55		+125		°C
Storage Temperature	TSTG		-65		+150		°C
Signal Voltage Relative to GND	VG		-0.5		7.0		V
Junction Temperature	TJ				150		°C
Supply Voltage	VCC		-0.5		7.0		V
Parameter
Flash Data Retention				20 years
Flash Endurance (write/erase cycles)			100,000 min

NOTE:

1.Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability.

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Max	Unit
Supply Voltage	VCC	4.5	5.5	V
Input High Voltage	VIH	2.2	VCC + 0.3	V
Input Low Voltage	VIL	-0.5	+0.8	V

SRAM TRUTH TABLE

SCS	OE	SWE	Mode	Data I/O	Power
H	X	X	Standby	High Z	Standby
L	L	H	Read	Data Out	Active
L	H	H	Read	High Z	Active
L	X	L	Write	Data In	Active

NOTE:

1.FCS must remain high when SCS is low.

CAPACITANCE

(TA = +25°C)

Test							Symbol	Condition	Max	Unit
	OE	Capacitance					COE	VIN = 0V, f = 1.0MHz	80	pF
F/S			WE			1-4 Capacitance	CWE	VIN = 0V, f = 1.0MHz	30	pF
F/S				CS	Capacitance		CCS	VIN = 0V, f = 1.0MHz	50	pF
D0-31 Capacitance							CI/O	VIN = 0V, f = 1.0MHz	30	pF
A0 - A16 Capacitance							CAD	VIN = 0V, f = 1.0MHz	80	pF

This parameter is guaranteed by design but not tested.

DC CHARACTERISTICS

(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)

Parameter

Symbol

Conditions

Min

Max

Unit

Input Leakage Current

ILI

VCC = 5.5, VIN = GND to VCC

10

µA

Output Leakage Current

ILO

SCS = VIH, OE = VIH, VOUT = GND to VCC

10

µA

SRAM Operating Supply Current x 32 Mode

ICCx32

SCS = VIL, OE = FCS = VIH, f = 5MHz, VCC = 5.5

620

mA

Standby Current

ISB

FCS = SCS = VIH, OE = VIH, f = 5MHz, VCC = 5.5

80

mA

SRAM Output Low Voltage

VOL

IOL = 8mA, VCC = 4.5

0.4

V

SRAM Output High Voltage

VOH

IOH = -4.0mA, VCC = 4.5

2.4

V

Flash VCC Active Current for Read (1)

ICC1

FCS = VIL, OE = SCS = VIH

260

mA

Flash VCC Active Current for Program or

ICC2

FCS = VIL, OE = SCS = VIH

300

mA

Erase (2)

Flash Output Low Voltage

VOL

IOL = 8.0mA, VCC = 4.5

0.45

V

Flash Output High Voltage

VOH1

IOH = -2.5 mA, VCC = 4.5

0.85 x VCC

V

Flash Output High Voltage

VOH2

IOH = -100 µA, VCC = 4.5

VCC -0.4

V

Flash Low VCC Lock Out Voltage

VLKO

3.2

4.2

V

NOTES:

1.The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH.

2.ICC active while Embedded Algorithm (program or erase) is in progress.

3.DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V

3White Electronic Designs Corporation • [phone] • www.whiteedc.com

White Electronic Designs

WSF41632-22XX

SRAM AC CHARACTERISTICS

(VCC = 5.0V, TA = -55°C TO +125°C)

Parameter	Symbol	-25			Unit
Read Cycle		Min		Max
Read Cycle Time	tRC	25			ns
Address Access Time	tAA			25	ns
Output Hold from Address Change	tOH	0			ns
Chip Select Access Time	tACS			25	ns
Output Enable to Output Valid	tOE			15	ns
Chip Select to Output in Low Z	tCLZ1	3			ns
Output Enable to Output in Low Z	tOLZ1	0			ns
Chip Disable to Output in High Z	tCHZ1			12	ns
Output Disable to Output in High Z	tOHZ1			12	ns

1. This parameter is guaranteed by design but not tested.

SRAM AC CHARACTERISTICS

(VCC = 5.0V, TA = -55°C TO +125°C)

Parameter	Symbol	-25			Unit
Write Cycle		Min		Max
Write Cycle Time	tWC	25			ns
Chip Select to End of Write	tCW	20			ns
Address Valid to End of Write	tAW	20			ns
Data Valid to End of Write	tDW	15			ns
Write Pulse Width	tWP	20			ns
Address Setup Time	tAS	3			ns
Address Hold Time	tAH	0			ns
Output Active from End of Write	tOW1	3			ns
Write Enable to Output in High Z	tWHZ1			15	ns
Data Hold from Write Time	tDH	0			ns

1. This parameter is guaranteed by design but not tested.

FIG. 2 AC TEST CIRCUIT

IOL

Current Source

D.U.T.	VZ ≈ 1.5V
Ceff = 50 pf	(Bipolar Supply)

IOH

Current Source

AC TEST CONDITIONS

Parameter	Typ	Unit
Input Pulse Levels	VIL = 0, VIH = 3.0	V
Input Rise and Fall	5	ns
Input and Output Reference Level	1.5	V
Output Timing Reference Level	1.5	V

Notes:

VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 W.

VZ is typically the midpoint of VOH and VOL.

IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.

White Electronic Designs Corporation • Phoenix AZ • [phone]

4

White Electronic Designs

WSF41632-22XX

FIG. 3 SRAM
TIMING WAVEFORM - READ CYCLE				tRC
		ADDRESS
			tAA
		SCS
		tRC	tACS	tCHZ
ADDRESS
		tAA	tCLZ
		SOE
	tOH		tOE	tOHZ
			tOLZ
DATA I/O	PREVIOUS DATA VALID	DATA VALID
		DATA I/O		DATA VALID
			HIGH IMPEDANCE
	READ CYCLE 1, (SCS = OE = VIL, SWE = FCS = VIH)		READ CYCLE 2, (SWE = FCS = VIH)

FIG. 4 SRAM

WRITE CYCLE - SWE CONTROLLED

	tWC
ADDRESS
tAW		tAH
	tCW
SCS
tAS	tWP
SWE		tOW
tWHZ	tDW	tDH
DATA I/O	DATA VALID

WRITE CYCLE 1, SWE CONTROLLED (FCS = VIH)

FIG. 5 SRAM

WRITE CYCLE - SCS CONTROLLED

tWC

ADDRESS

	tAS	tAW	tAH
		tCW
	SCS
		tWP
	SWE
		tDW	tDH

DATA I/O		DATA VALID

WRITE CYCLE 2, SCS CONTROLLED (FCS = VIH)

5White Electronic Designs Corporation • [phone] • www.whiteedc.com