White Electronic Designs WF512K32N-90H1M5A, WF512K32N-90H1M5, WF512K32N-90H1I5A, WF512K32N-90H1I5, WF512K32N-90H1C5A Datasheet

WF512K32-XXX5

HI-RELIABILITY PRODUCT

512Kx32 5V FLASH MODULE, SMD 5962-94612

FEATURES

■Access Times of 60, 70, 90, 120, 150ns

■Packaging

•66 pin, PGA Type, 1.075" square, Hermetic Ceramic HIP (Package 400(1))

•68 lead, 40mm, Low Capacitance Hermetic CQFP (Package 501)

•68 lead, 40mm, Low Profile 3.5mm (0.140"), CQFP (Package 502)

•68 lead, 22.4mm (0.880") Low Profile CQFP (G2U), 3.5mm (0.140") high, (Package 510)

•68 lead, 23.9mm (0.940") Low Profile CQFP (G1U), 3.5mm (0.140") high, (Package 519)

■100,000 Erase/Program Cycles Minimum

■Sector Architecture

•8 equal size sectors of 64KBytes each

•Any combination of sectors can be concurrently erased. Also supports full chip erase

■Organized as 512Kx32

■Commercial, Industrial and Military Temperature Ranges

■5 Volt Programming. 5V ± 10% Supply.

■Low Power CMOS, 6.5mA Standby

■Embedded Erase and Program Algorithms

■TTL Compatible Inputs and CMOS Outputs

■Built-in Decoupling Caps for Low Noise Operation

■Page Program Operation and Internal Program Control Time

■Weight

WF512K32-XG2UX5 - 8 grams typical WF512K32-XH1X5 - 13 grams typical WF512K32-XG4X5 - 20 grams typical WF512K32-XG4TX5 - 20 grams typical WF512K32-XG1UX5 - 5 grams typical

1.Call factory for PGA type (HIP) package options.

Note: See Flash Programming Application Note 4M5 for algorithms.

FIG. 1 PIN CONFIGURATION FOR WF512K32N-XH1X5
		TOP VIEW							PIN DESCRIPTION
1	12	23		34	45		56		I/O0-31 Data Inputs/Outputs
I/O8	WE2	I/O15	I/O24		VCC	I/O31			A0-18	Address Inputs
I/O9	CS2	I/O14	I/O25		CS4	I/O30			WE1-4	Write Enables
I/O10	GND	I/O13	I/O26		WE4	I/O29			CS1-4	Chip Selects
									OE	Output Enable
A14	I/O11	I/O12	A7		I/O27	I/O28			VCC	Power Supply
A16	A10	OE	A12		A4	A1			GND	Ground
A11	A9	A17	NC		A5	A2			NC	Not Connected
A0	A15	WE1	A13		A6	A3		BLOCK DIAGRAM
A18	VCC	I/O7	A8		WE3	I/O23	WE1 CS1	WE2 CS2	WE3 CS3	WE4 CS4
							OE
I/O0	CS1	I/O6	I/O16		CS3	I/O22	A 0 - 18
I/O1	NC	I/O5	I/O17		GND	I/O21	512K x 8	512K x 8	512K x 8	512K x 8
I/O2	I/O3	I/O4	I/O18		I/O19	I/O20
							8	8	8	8
11	22	33		44	55		66
							I/O 0 - 7	I/O 8 - 15	I/O 16 - 23	I/O 24 - 31

April 2001 Rev. 4

1

White Electronic Designs Corporation • Phoenix, AZ • [phone]

WF512K32-XXX5

FIG. 2 PIN CONFIGURATION FOR WF512K32F-XG4X5 (Low Capacitance)

AND WF512K32-XG4TX5

TOP VIEW

PIN DESCRIPTION

NC

A0

A1

A2

A3

A4

A5

CS1

GND

CS3

WE A6

A7

A8

A9

A10

VCC

I/O0-31

Data Inputs/Outputs

A0-18

Address Inputs

9

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

WE

Write Enable

Chip Selects

I/O0

10

60

I/O16

CS

1-4

I/O1

11

59

I/O17

OE

Output Enable

I/O2

12

58

I/O18

I/O3

13

57

I/O19

VCC

Power Supply

I/O4

14

56

I/O20

GND

Ground

I/O5

15

55

I/O21

I/O6

16

54

I/O22

NC

Not Connected

I/O7

17

53

I/O23

GND

18

52

GND

BLOCK DIAGRAM

I/O8

19

51

I/O24

I/O9

20

50

I/O25

CS 1

CS 2

CS 3

CS 4

I/O10

21

49

I/O26

WE

I/O11

22

48

I/O27

OE

47

I/O28

I/O12

23

A 0 - 1 8

I/O13

24

46

I/O29

I/O14

25

45

I/O30

512K x 8

512K x 8

512K x 8

512K x 8

I/O15

26

44

I/O31

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

8

8

8

8

VCC

A11

A12

A13

A14

A15

A16

CS2

OE

CS4

A17

A18

NC

NC

NC

NC

NC

I/O 0 - 7

I/O 8 - 1 5

I/O 16 - 23

I/O 24 - 31

FIG. 3 PIN CONFIGURATION FOR WF512K32-XG2UX5 AND WF512K32-XG1UX5

TOP VIEW

NC

A0

A1

A2

A3

A4

A5

CS3

GND

CS4

WE1

A6

A7

A8

A9

A10

VCC

9

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

I/O0

10

60

I/O16

I/O1

11

59

I/O17

I/O2

12

58

I/O18

I/O3

13

57

I/O19

I/O4

14

56

I/O20

I/O5

15

55

I/O21

I/O6

16

54

I/O22

I/O7

17

53

I/O23

GND

18

52

GND

I/O8

19

51

I/O24

I/O9

20

50

I/O25

I/O10

21

49

I/O26

I/O11

22

48

I/O27

I/O12

23

47

I/O28

I/O13

24

46

I/O29

I/O14

25

45

I/O30

I/O15

26

44

I/O31

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

VCC

A11

A12

A13

A14

A15

A16

CS1

OE

CS2

A17

WE2

WE3

WE4

A18

NC

NC

PIN DESCRIPTION

	I/O0-31						Data Inputs/Outputs
		A0-18					Address Inputs
					1-4		Write Enables
	WE
				1-4			Chip Selects
		CS
							Output Enable
			OE
		VCC					Power Supply
		GND					Ground

BLOCK DIAGRAM

WE1 CS 1

WE2 CS 2

WE3 CS 3

WE4 CS4

OE

A 0 - 1 8

512K x 8

512K x 8

512K x 8

512K x 8

8	8	8	8
I/O 0 - 7	I/O 8 - 15	I/O 16 - 23	I/O 24 - 31

White Electronic Designs Corporation • Phoenix, AZ • [phone]

2

WF512K32-XXX5

ABSOLUTE MAXIMUM RATINGS (1)

Parameter		Unit
Operating Temperature	-55 to +125	°C
Supply Voltage Range (VCC)	-2.0 to +7.0	V
Signal voltage range (any pin except A9) (2)	-2.0 to +7.0	V
Storage Temperature Range	-65 to +150	°C
Lead Temperature (soldering, 10 seconds)	+300	°C
Data Retention (Mil Temp)	20 years
Endurance - write/erase cycles (Mil Temp)	100,000 cycles min.
A9 Voltage for sector protect (VID) (3)	-2.0 to +14.0	V

NOTES:

1.Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability.

2.Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may overshoot VSS to -2.0 V for periods of up to 20ns. Maximum DC voltage on output and I/O pins is VCC + 0.5V. During voltage transitions, outputs may overshoot to Vcc + 2.0 V for periods of up to 20ns.

3.Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 may overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage on A9 is +13.5V which may overshoot to 14.0 V for periods

up to 20ns.

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Max	Unit
Supply Voltage	VCC	4.5	5.5	V
Input High Voltage	VIH	2.0	VCC + 0.5	V
Input Low Voltage	VIL	-0.5	+0.8	V
Operating Temp. (Mil.)	TA	-55	+125	°C
Operating Temp. (Ind.)	TA	-40	+85	°C
A9 Voltage for Sector Protect	VID	11.5	12.5	V

CAPACITANCE

(TA = +25°C)

	Parameter					Symbol	Conditions	Max	Unit
					capacitance	COE	VIN = 0 V, f = 1.0 MHz	50	pF
	OE
					1-4 capacitance	CWE	VIN = 0 V, f = 1.0 MHz		pF
	WE
					HIP (PGA)			20
					CQFP G4T			50
					CQFP G2U/G1U			15
			1-4 capacitance			CCS	VIN = 0 V, f = 1.0 MHz	20	pF
		CS
	Data I/O capacitance					CI/O	VI/O = 0 V, f = 1.0 MHz	20	pF
	Address input capacitance					CAD	VIN = 0 V, f = 1.0 MHz	50	pF

This parameter is guaranteed by design but not tested.

LOW CAPACITANCE CQFP

(TA = +25°C)

	Parameter				Symbol	Conditions	Max	Unit
				capacitance	COE	VIN = 0 V, f = 1.0 MHz	32	pF
	OE
	CQFP G4 capacitance				CWE	VIN = 0 V, f = 1.0 MHz	32	pF
					CCS	VIN = 0 V, f = 1.0 MHz	15	pF
		CS	1-4 capacitance
	Data I/O capacitance				CI/O	VI/O = 0 V, f = 1.0 MHz	15	pF
	Address input
	capacitance				CAD	VIN = 0 V, f = 1.0 MHz	32	pF

This parameter is guaranteed by design but not tested.

DC CHARACTERISTICS - CMOS COMPATIBLE

(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)

Parameter

Symbol

Conditions

Min

Max

Unit

Input Leakage Current

ILI

VCC = 5.5, VIN = GND or VCC

10

A

Output Leakage Current

ILOx32

VCC = 5.5, VIN = GND or VCC

10

A

VCC Active Current for Read (1)

ICC1

= VIL,

= VIH, f = 5MHz

190

mA

CS

OE

VCC Active Current for Program or Erase (2)

ICC2

= VIL,

= VIH

240

mA

CS

OE

VCC Standby Current

ICC4

VCC = 5.5, CS = VIH, f = 5MHz

6.5

mA

VCC Static Current

ICC3

VCC = 5.5, CS = VIH

0.6

mA

Output Low Voltage

VOL

IOL = 8.0 mA, VCC = 4.5

0.45

V

Output High Voltage

VOH1

IOH = 2.5 mA, VCC = 4.5

0.85 X VCC

V

Low VCC Lock-Out Voltage

VLKO

3.2

4.2

V

DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V

NOTES:

1.The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH.

2.ICC active while Embedded Algorithm (program or erase) is in progress.

3	White Electronic Designs Corporation • Phoenix, AZ • [phone]

WF512K32-XXX5

AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED

(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)

Parameter	Symbol		-60				-70			-90			-120		-150			Unit
			Min		Max	Min		Max	Min		Max	Min		Max	Min		Max
Write Cycle Time	tAVAV	tWC	60			70			90			120			150			ns
Write Enable Setup Time	tWLEL	tWS	0			0			0			0			0			ns
Chip Select Pulse Width	tELEH	tCP	40			45			45			50			50			ns
Address Setup Time	tAVEL	tAS	0			0			0			0			0			ns
Data Setup Time	tDVEH	tDS	40			45			45			50			50			ns
Data Hold Time	tEHDX	tDH	0			0			0			0			0			ns
Address Hold Time	tELAX	tAH	40			45			45			50			50			ns
Chip Select Pulse Width High	tEHEL	tCPH	20			20			20			20			20			ns
Duration of Byte Programming Operation (1)	tWHWH1				300			300			300			300			300	µs
Sector Erase Time (2)	tWHWH2				15			15			15			15			15	sec
Read Recovery Time	tGHEL		0			0			0			0			0			ns
Chip Programming Time					11			11			11			11			11	sec
Chip Erase Time (3)					64			64			64			64			64	sec

NOTES:

1.Typical value for tWHWH1 is 7µs.

2.Typical value for tWHWH2 is 1sec.

3.Typical value for Chip Erase Time is 8sec.

	FIG. 4				AC TEST CONDITIONS
	AC TEST CIRCUIT
		I OL			Parameter	Typ	Unit
	Current Source				Input Pulse Levels	VIL = 0, VIH = 3.0	V
					Input Rise and Fall	5	ns
					Input and Output Reference Level	1.5	V
	D.U.T.		VZ ≈1.5V		Output Timing Reference Level	1.5	V
	Ceff = 50 pf		(Bipolar Supply)	NOTES:
				VZ is programmable from -2V to +7V.
				IOL & IOH programmable from 0 to 16mA.
				Tester Impedance Z0 = 75 Ω.
		IOH		VZ is typically the midpoint of VOH and VOL.
	Current Source			IOL & IOH are adjusted to simulate a typical resistive load circuit.
				ATE tester includes jig capacitance.
White Electronic Designs Corporation • Phoenix, AZ • [phone]			4

WF512K32-XXX5

AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, WE CONTROLLED

(VCC = 5.0V, TA = -55°C to +125°C)

Parameter	Symbol			-60				-70			-90		-120			-150		Unit
				Min		Max	Min		Max	Min		Max	Min		Max	Min Max
Write Cycle Time	tAVAV		tWC	60			70			90			120			150		ns
Chip Select Setup Time	tELWL		tCS	0			0			0			0			0		ns
Write Enable Pulse Width	tWLWH		tWP	40			45			45			50			50		ns
Address Setup Time	tAVWH		tAS	0			0			0			0			0		ns
Data Setup Time	tDVWH		tDS	40			45			45			50			50		ns
Data Hold Time	tWHDX		tDH	0			0			0			0			0		ns
Address Hold Time	tWHAX		tAH	40			45			45			50			50		ns
Write Enable Pulse Width High	tWHWL		tWPH	20			20			20			20			20		ns
Duration of Byte Programming Operation (1)	tWHWH1					300			300			300			300		300	s
Sector Erase Time (2)	tWHWH2					15			15			15			15		15	sec
Read Recovery Time before Write	tGHWL			0			0			0			0			0		ns
VCC Set-up Time			tVCS	50			50			50			50			50		s
Chip Programming Time						11			11			11			11		11	sec
Output Enable Setup Time			tOES	0			0			0			0			0		ns
Output Enable Hold Time (4)			tOEH	10			10			10			10			10		ns
Chip Erase Time (3)						64			64			64			64		64	sec

NOTES:

1.Typical value for tWHWH1 is 7 s.

2.Typical value for tWHWH2 is 1sec.

3.Typical value for Chip Erase Time is 8sec.

4.For Toggle and Data Polling.

AC CHARACTERISTICS – READ ONLY OPERATIONS

(VCC = 5.0V, TA = -55°C to +125°C)

Parameter					Symbol			-60			-70			-90			-120		-150			Unit
							Min		Max	Min		Max	Min		Max	Min		Max	Min		Max
Read Cycle Time					tAVAV	tRC	60			70			90			120			150			ns
Address Access Time					tAVQV	tACC			60			70			90			120			150	ns
Chip Select Access Time					tELQV	tCE			60			70			90			120			150	ns
Output Enable to Output Valid					tGLQV	tOE			30			35			35			50			55	ns
Chip Select to Output High Z (1)					tEHQZ	tDF			20			20			20			30			35	ns
Output Enable High to Output High Z (1)					tGHQZ	tDF			20			20			20			30			35	ns
Output Hold from Address,		or		Change,	tAXQX	tOH	0			0			0			0			0			ns
	CS		OE
whichever is First
1. Guaranteed by design, but not tested

5	White Electronic Designs Corporation • Phoenix, AZ • [phone]