White Electronic Designs WS512K16-25FLIA, WS512K16-25FLI, WS512K16-25FLCA, WS512K16-25FLC, WS512K16-25DLMA Datasheet

WS512K16-XXX

512Kx16 SRAM MODULE ADVANCED*

FEATURES

■Access Times 17, 20, 25, 35ns

■MIL-STD-883 Compliant Devices Available

■Packaging

•44 pin Ceramic SOJ (Package 102)

• 44 lead Ceramic Flatpack (Package 209)

■Organized as two banks of 256Kx16

■Data Byte Control:

Lower Byte (LB) = I/O1-8

Upper Byte (UB) = I/O9-16

■Data I/O Compatible with 3.3V devices

■2V Minimum Data Retention for battery back up operation

■Commercial, Industrial and Military Temperature Range

■5 Volt Power Supply (3.3V parts also available)

■Low Power CMOS

■TTL Compatible Inputs and Outputs

* This data sheet describes a product that may or may not be under development and is subject to change or cancellation without notice.

PIN CONFIGURATION FOR WS512K16-XXX

44 CSOJ

PIN DESCRIPTION

44 FLATPACK

A0-17

Address Inputs

TOP VIEW

Lower-Byte Control (I/O1-8)

LB

Upper-Byte Control (I/O9-16)

A0

1

44

A17

UB

A1

2

43

A16

I/O1-16

Data Input/Output

A2

3

42

A15

1-2

Chip Select

A3

4

41

OE

CS

A4

5

40

UB

OE

Output Enable

6

39

CS1

LB

Write Enable

I/O1

7

38

I/O16

WE

I/O2

8

37

I/O15

VCC

+5.0V Power

I/O3

9

36

I/O14

GND

Ground

I/O4

10

35

I/O13

VCC

11

34

GND

NC

No Connection

GND

12

33

VCC

I/O5

13

32

I/O12

I/O6

14

31

I/O11

I/O7

15

30

I/O10

BLOCK DIAGRAM

I/O8

16

29

I/O9

17

28

WE

CS2

A 0 - 1 7

A5

18

27

A14

WE

A6

19

26

A13

OE

A7

20

25

A12

UB

A8

21

24

A11

LB

A9

22

23

A10

256K x 16

256K x 16

1

CS

CS

2

I/O 1 - 1 6

3

MONOLITHICS SRAM

April 1998

1

White Microelectronics • Phoenix, AZ • [phone]

WS512K16-XXX

3

MONOLITHICS SRAM

TRUTH TABLE

CS1

CS2

WE

OE

LB

UB

Mode

Data I/O

Power

I/O1-8

I/O9-16

H

H

X

X

X

X

Not Select

High Z

High Z

Standby

L

H

H

H

X

X

H

L

Output Disable

High Z

High Z

Active

L

H

X

X

H

H

H

L

H

L

L

H

Data Out

High Z

H

L

H

L

Read

High Z

Data Out

Active

L

H

L

L

Data Out

Data Out

H

L

L

H

Data In

High Z

L

X

H

L

Write

High Z

Data In

Active

L

H

L

L

Data In

Data In

ABSOLUTE MAXIMUM RATINGS

Parameter	Symbol	Min	Max	Unit
Operating Temperature	TA	-55	+125	°C
Storage Temperature	TSTG	-65	+150	°C
Signal Voltage Relative to GND	VG	-0.5	Vcc+0.5	V
Junction Temperature	TJ		150	°C
Supply Voltage	VCC	-0.5	7.0	V

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Max	Unit
Supply Voltage	VCC	4.5	5.5	V
Input High Voltage	VIH	2.2	VCC + 0.3	V
Input Low Voltage	VIL	-0.3	+0.8	V
Operating Temp. (Mil.)	TA	-55	+125	°C

CAPACITANCE

(TA = +25°C)

Parameter	Symbol	Condition	Max	Unit
Input capacitance	CIN	VIN = 0V, f = 1.0MHz	25	pF
Output capicitance	COUT	VOUT = 0V, f = 1.0MHz	25	pF

This parameter is guaranteed by design but not tested.

DC CHARACTERISTICS

(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)

Parameter

Sym

Conditions

Min

Max

Units

Input Leakage Current

ILI

VCC = 5.5, VIN = GND to VCC

10

mA

Output Leakage Current

ILO

= VIH,

= VIH, VOUT = GND to VCC

10

mA

CS

OE

Operating Supply Current

ICC

= VIL,

= VIH, f = 5MHz, Vcc = 5.5

290

mA

CS

OE

Standby Current

ISB

= VIH,

= VIH, f = 5MHz, Vcc = 5.5

30

mA

CS

OE

Output Low Voltage

VOL

IOL = 8mA, VCC = 4.5

0.4

V

Output High Voltage

VOH

IOH = -4.0mA, VCC = 4.5

2.4

V

NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V

DATA RETENTION CHARACTERISTICS

(TA = -55°C to +125°C)

Parameter	Symbol		Conditions					Units
					Min	Typ	Max
Data Retention Supply Voltage	VDR		CS	³ VCC -0.2V	2.0		5.5	V
Data Retention Current	ICCDR1			VCC = 3V		2.0	12.0*	mA

* Also available in Low Power version. Please call factory for informaion.

White Microelectronics • Phoenix, AZ • [phone]

2