WSF256K8-XCX
256Kx8 SRAM/ FLASH MODULE
FIG. 1
PIN CONFIGURATION
TOP VIEW
A18 |
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1 |
32 |
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VCC |
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A16 |
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2 |
31 |
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WE |
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A15 |
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3 |
30 |
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A17 |
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A12 |
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4 |
29 |
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A14 |
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A7 |
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5 |
28 |
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A13 |
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A6 |
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6 |
27 |
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A8 |
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A5 |
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7 |
26 |
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A9 |
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A4 |
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8 |
25 |
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A11 |
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A3 |
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9 |
24 |
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OE |
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A2 |
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10 |
23 |
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A10 |
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A1 |
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11 |
22 |
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CS |
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A0 |
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12 |
21 |
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I/O7 |
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I/O0 |
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13 |
20 |
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I/O6 |
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I/O1 |
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14 |
19 |
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I/O5 |
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I/O2 |
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15 |
18 |
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I/O4 |
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VSS |
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16 |
17 |
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I/O3 |
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PIN DESCRIPTION
A0-18 |
Address Inputs |
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I/O0-7 |
Data Input/Output |
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Chip Select |
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CS |
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Output Enable |
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OE |
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Write Enable |
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WE |
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VCC |
+5.0V Power |
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VSS |
Ground |
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BLOCK DIAGRAM
A0-16
I/O0-7
WE
OE
ADVANCED*
FEATURES
■Access Times of 35ns (SRAM) and 70ns (FLASH)
■JEDEC Standard, Hermetic Ceramic Package, 32 pin DIP (Package 300)
■256Kx8 SRAM
■256Kx8 5V FLASH
■Memory Map
Flash Memory: 0H-3FFFFH
SRAM: 40000H-7FFFFH
■Low Power CMOS
■Commercial, Industrial and Military Temperature Ranges
■TTL Compatible Inputs and Outputs
■Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation
FLASH MEMORY FEATURES
■10,000 Erase/Program Cycles
■Sector Architecture
•8 equal size sectors of 16KBytes each
•Any combination of sectors can be concurrently erased. Also supports full chip erase
■Data Retention, 10 Years at 125°C
■5 Volt Programming; 5V ± 10% Supply
■Embedded Erase and Program Algorithms
■Hardware and Software Write Protection
■Page Program Operation and Internal Program Control Time
*This data sheet describes a product that may or may not be under development and is subject to change or cancellation without notice.
128K x 8 |
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128K x 8 |
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128K x 8 |
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128K x 8 |
Flash |
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Flash |
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SRAM |
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SRAM |
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A17
Decoder
A18
CS
11
MODULES MIXED
January 1996 |
1 |
White Microelectronics • Phoenix, AZ • (602) 437-1520 |