White Electronic Designs WSE128K16-73H1MA, WSE128K16-73H1M, WSE128K16-73H1IA, WSE128K16-73H1I, WSE128K16-73H1CA Datasheet

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128KX16 SRAM/EEPROM MODULE

FEATURES

■Access Times of 35ns (SRAM) and 150ns (EEPROM)

■Access Times of 45ns (SRAM) and 120ns (EEPROM)

■Access Times of 70ns (SRAM) and 300ns (EEPROM)

■Packaging

•66 pin, PGA Type, 1.075" square HIP, Hermetic Ceramic HIP (H1) (Package 400)

•68 lead, Hermetic CQFP (G2T), 22mm (0.880") square (Package 509). Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 2)

■128Kx16 SRAM

■128Kx16 EEPROM

■Organized as 128Kx16 of SRAM and 128Kx16 of EEPROM Memory with separate Data Buses

■Both blocks of memory are User Configurable as 256Kx8

■Low Power CMOS

■Commercial, Industrial and Military Temperature Ranges

WSE128K16-XXX

PRELIMINARY*

■TTL Compatible Inputs and Outputs

■Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation

■Weight - 13 grams typical

EEPROM MEMORY FEATURES

■Write Endurance 10,000 Cycles

■Data Retention at 25°C, 10 Years

■Low Power CMOS Operation

■Automatic Page Write Operation

■Page Write Cycle Time 10ms Max.

■Data Polling for End of Write Detection

■Hardware and Software Data Protection

■TTL Compatible Inputs and Outputs

*This data sheet describes a product under development, not fully characterized, and is subject to change without notice.

FIG.1

PIN CONFIGURATION FOR WSE128K16-XH1X

PIN DESCRIPTION

TOP VIEW

ED0-15

EEPROM Data Inputs/Outputs

SD0-15

SRAM Data Inputs/Outputs

SD8

SWE2

SD15

ED8

VCC

ED15

A0-16

Address Inputs

1-2

SRAM Write Enable

SD9

SCS2

SD14

ED9

ECS2

ED14

SWE

1-2

SRAM Chip Selects

SD10

GND

SD13

ED10

EWE2

ED13

SCS

Output Enable

A13

SD11

SD12

ED11

ED12

VCC

Power Supply

A14

A10

GND

Ground

A15

A11

Not Connected

1-2

EEPROM Write Enable

A16

A12

SWE1

EWE

1-2

EEPROM Chip Select

VCC

SD7

EWE1

ED7

ECS

BLOCK DIAGRAM

SD0

SCS1

SD6

ED0

ECS1

ED6

SWE1 SCS1 SWE

2 SCS2

EWE

ECS1

EWE

ECS2

SD1

SD5

ED1

GND

ED5

SD2

SD3

SD4

ED2

ED3

ED4

A 0 - 1 6

128K x 8

SRAM

EEPROM

SD 0 - 7

SD 8 - 1 5

ED 0 - 7

ED 8 - 1 5

May 2001, Rev. 4

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

WSE128K16-XXX

	FIG. 2 PIN CONFIGURATION FOR WSE128K16-XG2TX	PIN DESCRIPTION
	TOP VIEW	PIN DESCRIPTION
	TOP VIEW

ECS1

GND

ECS2

SWE1

A10

VCC

68 67 66 65 64 63 62 61

SD0

ED0

SD1

ED1

SD2

ED2

SD3

ED3

SD4

ED4

SD5

ED5

SD6

ED6

SD7

ED7

GND

SD8

ED8

SD9

ED9

SD10

ED10

SD11

ED11

SD12

ED12

SD13

ED13

SD14

ED14

SD15

ED15

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

VCC

A11

A12

A13

A14

A15

A16

SCS1

SCS2

SWE2

EWE1

EWE2

0.940"

The WEDC 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form.

			ED0-15					EEPROM Data Inputs/Outputs

			SD0-15					SRAM Data Inputs/Outputs
			A0-16					Address Inputs
								SRAM Write Enable
SWE					1-2
								SRAM Chip Selects
		SCS				1-2
								Output Enable
				OE
			VCC					Power Supply
			GND					Ground
			NC					Not Connected
							1-2	EEPROM Write Enable
	EWE
								EEPROM Chip Select
			ECS				1-2

BLOCK DIAGRAM

SWE1 SCS1

SWE

2 SCS2

EWE

ECS1

EWE

ECS2

A 0 - 1 6

128K x 8

SRAM

EEPROM

SD 0 - 7

SD 8 - 1 5

ED 0 - 7

ED 8 - 1 5

White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520

WSE128K16-XXX

ABSOLUTE MAXIMUM RATINGS

Parameter	Symbol	Min	Max	Unit

Operating Temperature	TA	-55	+125	°C

Storage Temperature	TSTG	-65	+150	°C

Signal Voltage Relative to GND	VG	-0.5	Vcc+0.5	V

Junction Temperature	TJ		150	°C

Supply Voltage	VCC	-0.5	7.0	V

CAPACITANCE

(TA = +25°C)

Parameter				Symbol	Conditions	Max	Unit
			capacitance	COE	VIN = 0 V, f = 1.0 MHz	50	pF
OE			capacitance	COE	VIN = 0 V, f = 1.0 MHz	50	pF
			1-4 capacitance	CWE	VIN = 0 V, f = 1.0 MHz		pF
WE			1-4 capacitance	CWE	VIN = 0 V, f = 1.0 MHz		pF
			HIP (PGA)			20
			CQFP G2T			20
		1-4 capacitance		CCS	VIN = 0 V, f = 1.0 MHz	20	pF
	CS	1-4 capacitance		CCS	VIN = 0 V, f = 1.0 MHz	20	pF
Data I/O capacitance				CI/O	VI/O = 0 V, f = 1.0 MHz	20	pF
Address input capacitance				CAD	VIN = 0 V, f = 1.0 MHz	50	pF

This parameter is guaranteed by design but not tested.

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Max	Unit
Supply Voltage	VCC	4.5	5.5	V
Input High Voltage	VIH	2.0	VCC + 0.3	V
Input Low Voltage	VIL	-0.3	+0.8	V
Operating Temp. (Mil.)	TA	-55	+125	°C

EEPROM TRUTH TABLE


CS	OE	WE	Mode	Data I/O
H	X	X	Standby	High Z
L	L	H	Read	Data Out
L	H	L	Write	Data In
X	H	X	Out Disable	High Z/Data Out
X	X	H	Write
X	L	X	Inhibit

SRAM TRUTH TABLE


SCS	OE		SWE		Mode	Data I/O	Power
H		X		X	Standby	High Z	Standby
L		L		H	Read	Data Out	Active
L		H		H	Read	High Z	Active
L		X		L	Write	Data In	Active

DC CHARACTERISTICS

(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)

Parameter

Symbol

Conditions

Min

Max

Unit

Input Leakage Current

ILI

VCC = 5.5, VIN = GND to VCC

Output Leakage Current

ILO

= VIH,

= VIH, VOUT = GND to VCC

SCS

SRAM Operating Supply Current x 16 Mode

ICCx16

= VIL,

= VIH, f = 5MHz, VCC = 5.5

360

SCS

ECS

Standby Current

ISB

= VIH,

= VIH, f = 5MHz, VCC = 5.5

31.2

ECS

SCS

(35 to 45ns)

VOL

IOL = 8.0mA, VCC = 4.5

0.4

SRAM Output Low Voltage

(70ns)

VOL

IOL = 2.1mA, VCC = 4.5

0.4

(35 to 45ns)

VOH

IOH = -4.0mA, VCC = 4.5

2.4

SRAM Output High Voltage

(70ns)

VOH

IOH = -1mA, VCC = 4.5

2.4

EEPROM Operating Supply Current x 16 Mode

ICC1

= VIL,

= VIH

155

ECS

SCS

EEPROM Output Low Voltage

VOL

IOL = 2.1 mA, VCC = 4.5V

0.45

EEPROM Output High Voltage

VOH1

IOH = 400 A, VCC = 4.5V

2.4

NOTES:

1.The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH.

2.DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V

3	White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

WSE128K16-XXX

SRAM AC CHARACTERISTICS

(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)

Parameter	Symbol	-35		-45		-70		Units
Read Cycle		Min	Max	Min	Max	Min	Max
Read Cycle Time	tRC	35		45		70		ns
Address Access Time	tAA		35		45		70	ns
Output Hold from Address Change	tOH	0		0		3		ns
Chip Select Access Time	tACS		35		45		70	ns
Output Enable to Output Valid	tOE		20		25		35	ns
Chip Select to Output in Low Z	tCLZ1	3		3		3		ns
Output Enable to Output in Low Z	tOLZ1	0		0		0		ns
Chip Disable to Output in High Z	tCHZ1		20		20		25	ns
Output Disable to Output in High Z	tOHZ1		20		20		25	ns

1. This parameter is guaranteed by design but not tested.

SRAM AC CHARACTERISTICS

(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)

Parameter	Symbol		-35			-45			-70		Units
Write Cycle		Min		Max	Min		Max	Min		Max
Write Cycle Time	tWC	35			45			70			ns
Chip Select to End of Write	tCW	25			30			60			ns
Address Valid to End of Write	tAW	25			30			60			ns
Data Valid to End of Write	tDW	20			25			30			ns
Write Pulse Width	tWP	25			30			50			ns
Address Setup Time	tAS	0			0			5			ns
Address Hold Time	tAH	0			0			5			ns
Output Active from End of Write	tOW1	4			4			5			ns
Write Enable to Output in High Z	tWHZ1			20			25			25	ns
Data Hold Time	tDH	0			0			0			ns

1. This parameter is guaranteed by design but not tested.

FIG. 3

AC TEST CIRCUIT

I OL

Current Source

D.U.T.	VZ ≈1.5V
Ceff = 50 pf	(Bipolar Supply)
Ceff = 50 pf

IOH

Current Source

AC TEST CONDITIONS

Parameter	Typ	Unit
Input Pulse Levels	VIL = 0, VIH = 3.0	V

Input Rise and Fall	5	ns
Input and Output Reference Level	1.5	V

Output Timing Reference Level	1.5	V

NOTES:

VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω.

VZ is typically the midpoint of VOH and VOL.

IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.

White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520

White Electronic Designs WSE128K16-73H1MA, WSE128K16-73H1M, WSE128K16-73H1IA, WSE128K16-73H1I, WSE128K16-73H1CA Datasheet

					WSE128K16-XXX
FIG. 4	SRAM READ CYCLE				tRC
					tRC
			ADDRESS
				tAA
			SCS
	tRC			tACS	tCHZ
					tCHZ
ADDRESS
ADDRESS				tCLZ
	tAA			tCLZ
	tAA		SOE
			SOE
	tOH			tOE	tOHZ
SRAM			SRAM	tOLZ
DATA I/O	PREVIOUS DATA VALID	DATA VALID	DATA I/O	HIGH IMPEDANCE	DATA VALID
				HIGH IMPEDANCE
	READ CYCLE 1, (SCS = OE = VIL, SWE = VIH)			READ CYCLE 2, (SWE = VIH)

FIG. 5 SRAM WRITE CYCLE

SWE CONTROLLED

	tWC
ADDRESS
tAW		tAH
	tCW	tAH
	tCW
SCS
tAS	tWP
	tWP
SWE		tOW
		tOW
tWHZ	tDW	tDH
SRAM
DATA I/O	DATA VALID

WRITE CYCLE 1, SWE CONTROLLED

FIG. 6 SRAM WRITE CYCLE

SCS CONTROLLED

tWC

ADDRESS

tAS	tAW	tAH
tAS	tCW	tAH
	tCW
SCS
	tWP
SWE
	tDW	tDH

SRAM

DATA I/O		DATA VALID

WRITE CYCLE 2, SCS CONTROLLED

5	White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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