White Electronic Designs EDI88512LP70CC, EDI88512LP70CB, EDI88512LP100NM, EDI88512LP100NI, EDI88512LP100NC Datasheet

512Kx8 Monolithic SRAM CMOS

FEATURES

■512Kx8 bit CMOS Static

■Random Access Memory

•Access Times of 70, 85, 100ns

•Data Retention Function (LP version)

•TTL Compatible Inputs and Outputs

•Fully Static, No Clocks

■32 lead JEDEC Approved Evolutionary Pinout

•Ceramic Sidebrazed 600 mil DIP (Package 9)

•Ceramic SOJ (Package 140)

■Single +5V (±10%) Supply Operation

EDI88512C

HI-RELIABILITY PRODUCT

The EDI88512C is a 4 megabit Monolithic CMOS Static RAM.

The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. Both the DIP and CSOJ packages are pin for pin upgrades for the single chip enable 128K x 8, the EDI88128C. Pins 1 and 30 become the higher order addresses.

A Low Power version with Data Retention (EDI88512LP) is also available for battery backed applications. Military product is available compliant to Appendix A of MIL-PRF-38535.

FIG. 1 PIN CONFIGURATION

PIN DESCRIPTION

	TOP VIEW							I/O0-7	Data Inputs/Outputs
								A0-18	Address Inputs
A18	1	32	VCC					WE	Write Enables
A16	2	31	A15					CS	Chip Selects
A14	3	30	A17
A12	4	29	WE					OE	Output Enable
A7	5	28	A13
								VCC	Power (+5V ±10%)
A6	6	27	A8
A5	7	26	A9					VSS	Ground
A4	8	25	A11
A3	9	24	OE					NC	Not Connected
A2	10	23	A10		BLOCK DIAGRAM
A1	11	22	CS
AØ	12	21	I/O7
I/OØ	13	20	I/O6
I/O1	14	19	I/O5			Memory Array
I/O2	15	18	I/O4
VSS	16	17	I/O3
				AØ-18	Address	Address	I/O	I/OØ-7
					Buffer	Decoder	Circuits
				WE
				CS
				OE

February 2001 Rev. 11

1

White Electronic Designs Corporation • www.whiteedc.com • [phone]

EDI88512C

ABSOLUTE MAXIMUM RATINGS

Parameter		Unit
Voltage on any pin relative to Vss	-0.5 to 7.0	V
Operating Temperature TA (Ambient)
Commercial	0 to +70	°C
Industrial	-40 to +85	°C
Military	-55 to +125	°C
Storage Temperature, Plastic	-65 to +150	°C
Power Dissipation	1	W
Output Current	20	mA
Junction Temperature, TJ	175	°C

NOTE:

Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

TRUTH TABLE

OE

CS

WE

Mode

Output

Power

X

H

X

Standby

High Z

Icc2, Icc3

H

L

H

Output Deselect

High Z

Icc1

L

L

H

Read

Data Out

Icc1

X

L

L

Write

Data In

Icc1

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Typ	Max	Unit
Supply Voltage	VCC	4.5	5.0	5.5	V
Supply Voltage	VSS	0	0	0	V
Input High Voltage	VIH	2.2	—	Vcc +0.5	V
Input Low Voltage	VIL	-0.3	—	+0.8	V

CAPACITANCE

(TA = +25°C)

Parameter	Symbol	Condition	Max	Unit
Address Lines	CI	VIN = Vcc or Vss, f = 1.0MHz	12	pF
Data Lines	CO	VOUT = Vcc or Vss, f = 1.0MHz	14	pF

These parameters are sampled, not 100% tested.

DC CHARACTERISTICS

(VCC = 5V, *TA = -55°C to +125°C)

Parameter

Symbol

Conditions

Min

Typ*

Max

Units

Input Leakage Current

ILI

VIN = 0V to VCC

—

—

±10

A

Output Leakage Current

ILO

VI/O = 0V to VCC

—

—

±10

A

Operating Power Supply Current

ICC1

= VIL, II/O = 0mA, Min Cycle

(70-100ns)

—

45

75

mA

WE,

CS

Standby (TTL) Power Supply Current

ICC2

≥ VIH, VIN ≤ VIL, VIN ≥ VIH

—

3

10

mA

CS

Full Standby Power Supply Current

ICC3

≥ VCC -0.2V

C

—

—

5

mA

CS

VIN ≥ Vcc -0.2V or VIN ≤ 0.2V

LP

—

—

2

mA

Output Low Voltage

VOL

IOL = 2.1mA

—

—

0.4

V

Output High Voltage

VOH

IOH = -1.0mA

2.4

—

—

V

NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V

AC TEST CONDITIONS

Figure 1	Vcc	Figure 2	Vcc
	480Ω		480Ω
Q		Q
255Ω	30pF	255Ω	5pF

Input Pulse Levels	VSS to 3.0V
Input Rise and Fall Times	5ns
Input and Output Timing Levels	1.5V
Output Load	Figure 1

NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)

White Electronic Designs Corporation • Phoenix, AZ • [phone]

2

EDI88512C

AC CHARACTERISTICS – READ CYCLE

(VCC = 5.0V, VSS = 0V, TA = 0°C to +70°C)

Symbol

70ns

85ns

100ns

Parameter

JEDEC

Alt.

Min

Max

Min

Max

Min

Max

Units

Read Cycle Time

tAVAV

tRC

70

85

100

ns

Address Access Time

tAVQV

tAA

70

85

100

ns

Chip Enable Access Time

tELQV

tACS

70

85

100

ns

Chip Enable to Output in Low Z (1)

tELQX

tCLZ

10

10

10

ns

Chip Disable to Output in High Z (1)

tEHQZ

tCHZ

25

30

30

ns

Output Hold from Address Change

tAVQX

tOH

10

10

10

ns

Output Enable to Output Valid

tGLQV

tOE

35

45

50

ns

Output Enable to Output in Low Z (1)

tGLQX

tOLZ

5

5

5

ns

Output Disable to Output in High Z(1)

tGHQZ

tOHZ

0

25

0

30

0

30

ns

1. This parameter is guaranteed by design but not tested.

AC CHARACTERISTICS – WRITE CYCLE

(VCC = 5.0V, VSS = 0V, TA = 0°C to +70°C)

		Symbol			70ns			85ns			100ns
Parameter	JEDEC		Alt.	Min		Max	Min		Max	Min		Max	Units
Write Cycle Time	tAVAV		tWC	70			85			100			ns
Chip Enable to End of Write	tELWH		tCW	60			70			80			ns
	tELEH		tCW	60			70			80			ns
Address Setup Time	tAVWL		tAS	0			0			0			ns
	tAVEL		tAS	0			0			0			ns
Address Valid to End of Write	tAVWH		tAW	65			70			80			ns
	tAVEH		tAW	65			70			80			ns
Write Pulse Width	tWLWH		tWP	50			55			60			ns
	tWLEH		tWP	50			55			60			ns
Write Recovery Time	tWHAX		tWR	0			0			0			ns
	tEHAX		tWR	0			0			0			ns
Data Hold Time	tWHDX		tDH	0			0			0			ns
	tEHDX		tDH	0			0			0			ns
Write to Output in High Z (1)	tWLQZ		tWHZ	0		25	0		30	0		30	ns
Data to Write Time	tDVWH		tDW	40			40			40			ns
	tDVEH		tDW	30			35			40			ns
Output Active from End of Write (1)	tWHQX		tWLZ	5			5			5			ns

1. This parameter is guaranteed by design but not tested.

3	White Electronic Designs Corporation • Phoenix, AZ • [phone]