White Electronic Designs WED9LC6816V1312BC, WED9LC6816V1310BI, WED9LC6816V1310BC, WED9LC6816V2012BI, WED9LC6816V2012BC Datasheet

White Electronic Designs

WED9LC6816V

256Kx32 SSRAM/4Mx32 SDRAM

External Memory Solution for Texas Instruments TMS320C6000 DSP

FEATURES

νClock speeds:

•SSRAM: 200, 166,150, and 133 MHz

•SDRAMs: 125 and 100 MHz

νDSP Memory Solution

•Texas Instruments TMS320C6201

•Texas Instruments TMS320C6701

νPackaging:

•153 pin BGA, JEDEC MO-163

ν3.3V Operating supply voltage

νDirect control interface to both the SSRAM and SDRAM ports on the “C6x”

νCommon address and databus

ν65% space savings vs. monolithic solution

νReduced system inductance and capacitance

DESCRIPTION

The WED9LC6816V is a 3.3V, 256K x 32 Synchronous Pipeline SRAM and a 4Mx32 Synchronous DRAM array constructed with one 256K x 32 SBSRAM and two 4Mx16 SDRAM die mounted on a multilayer laminate substrate. The device is packaged in a 153 lead, 14mm by 22mm, BGA.

The WED9LC6816V provides a total memory solution for the Texas Instruments TMS320C6201 and the TMS320C6701 DSPs The Synchronous Pipeline SRAM is available with clock speeds of 200, 166,150,v and 133 MHz, allowing the user to develop a fast external memory for the SSRAM interface port .

The SDRAM is available in clock speeds of 125 and 100 MHz, allowing the user to develop a fast external memory for the SDRAM interface port.

The WED9LC6816V is available in both commercial and industrial temperature ranges.

FIG. 1 PIN CONFIGURATION

PIN DESCRIPTION

TOP VIEW

A0-17

Address Bus

1

2

3

4

5

6

7

8

9

DQ0-31

Data Bus

A

DQ19

DQ23

VCC

VSS

VSS

VSS

VCC

DQ24

DQ28

SSCLK

SSRAM Clock

B

DQ18

DQ22

VCC

VSS

VSS

VCC

DQ25

DQ29

SDCE

SSADC

SSRAM Address Status Control

C

VCCQ

VCCQ

VCC

SDWE

SDA10

NC

VCC

VCCQ

VCCQ

SSWE

SSRAM Write Enable

D

DQ17

DQ21

VCC

VSS

VSS

VSS

VCC

DQ26

DQ30

SSOE

SSRAM Output Enable

E

DQ16

DQ20

VCC

VSS

SDCLK

VSS

VCC

DQ27

DQ31

SDCLK

SDRAM Clock

F

VCCQ

VCCQ

VCC

VSS

VSS

VSS

VCC

VCCQ

VCCQ

SDRAS

SDRAM Row Address Strobe

G

NC

NC

NC

SDRAS

SDCAS

VSS

A2

A4

A5

SDCAS

SDRAM Column Address Strobe

H

NC

NC

A8

VSS

VSS

NC

A1

A3

A10

SDWE

SDRAM Write Enable

J

A6

A7

A9

VSS

VSS

NC

A0

A11

A12

SDA10

SDRAM Address10/auto precharge

K

A17

NC/A18

NC/A19

VSS

VSS

NC

NC

A13

A14

BWE0-3

SSRAM Byte Write Enables

L

NC

NC

NC

BWE

2

BWE3

NC

NC

A15

A16

SDRAM SDQM 0-3

M

VCCQ

VCCQ

VCC

BWE

0

BWE

3

NC

NC

A15

A16

SSCE

Chip Enable SSRAM Device

N

DQ12

DQ11

VCC

VSS

VSS

VSS

VCC

DQ4

DQ0

Chip Enable SDRAM Device

SDCE

P

DQ13

DQ10

VCC

VSS

SSCLK

VSS

VCC

DQ5

DQ1

VCC

Power Supply pins, 3.3V

R

VCCQ

VCCQ

VCC

VSS

VSS

VSS

Vcc

VCCQ

VCCQ

VCCQ

Data Bus Power Supply pins,

T

DQ14

DQ9

VCC

NC

VCC

DQ6

DQ2

3.3V (2.5V future)

SSADC

SSWE

U

DQ15

DQ8

VCC

NC

VCC

DQ7

DQ3

VSS

Ground

SSOE

SSCE

NC

No Contact

August 2002 Rev 0	1	White Electronic Designs Corporation • [phone] • www.whiteedc.com
ECO #14663

White Electronic Designs	WED9LC6816V
FIG. 2 BLOCK DIAGRAM

A0-17	A0
	A1
SSWE
BWE0
BWE1
BWE2
BWE3
SSCE
SSOE
SSADC
SSCLK
SDA10	A12
	A13
SDCE
SDRAS
SDCAS
SDWE
SDCLK
	A12
	A13

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

BWE

BW1

BW2

BW3

BW4

CE2

OE ADSC

CLK

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A11

A10/AP BA0 BA1 LDQM UDQM CS RAS CAS WE CLK

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A11

A10/AP BA0 BA1 LDQM UDQM CS RAS CAS WE CLK

DQ1-8 DQ0-7

DQ9-16 DQ8-15

DQ17-24 DQ16-23

DQ25-32 DQ24-31

DQ0-31

DQ0-7 DQ0-7

DQ8-15 DQ8-15

DQ0-7 DQ16-23

DQ8-15 DQ24-31

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White Electronic Designs

WED9LC6816V

OUTPUT FUNCTIONAL DESCRIPTIONS

Symbol

Type

Signal

Polarity

Function

SSCLK

Input

Pulse

Positive Edge

The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.

SSADS

When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define

SSOE

Input

Pulse

Active Low

the operation to be executed by the SSRAM.

SSWE

Input

Pulse

Active Low

disable or enable SSRAM device operation.

SSCE

SSCE

SDCLK

Input

Pulse

Positive Edge

The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.

SDCE

Input

Pulse

Active Low

SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE0-3.

SDRAS

When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define

SDCAS

Input

Pulse

Active Low

the operation to be executed by the SDRAM.

SDWE

Address bus for SSRAM and SDRAM

A0 and A1 are the burst address inputs for the SSRAM

During a Bank Active command cycle, A0-11, SDA10 defines the row address (RA0-10)

when sampled at the rising clock edge.

A0-17,

During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when

Input

Level

—

sampled at the rising clock edge. In addition to the row address, SDA10 is used to invoke

SDA10

Autoprecharge operation at the end of the Burst Read or Write Cycle. If SDA10 is high,

autoprecharge is selected and A12 and A13 define the bank to be precharged. If SDA10 is

low, autoprecharge is disabled.

During a Precharge command cycle, SDA10 is used in conjunction with A12 and A13 to

control which bank(s) to precharge. If SDA10 is high, all banks will be precharged regardless

of the state of A12 and A13. If SDA10 is low, then A12 and A13 are used to define which

bank to precharge.

DQ0-31

Input

Level

—

Data Input/Output are multiplexed on the same pins.

Output

BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the

BWE0-3

Input

Pulse

SDRAM. BWE0 is associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3

with DQ24-31.

VCC, VSS

Supply

Power and ground for the input buffers and the core logic.

VCCQ

Supply

Data base power supply pins, 3.3V (2.5V future).

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White Electronic Designs

WED9LC6816V

ABSOLUTE MAXIMUM RATINGS

Voltage on VCC Relative to VSS	-0.5V to +4.6V
Vin (DQx)	-0.5V to Vcc +0.5V
Storage Temperature (BGA)	-55°C to +125°C
Junction Temperature	+150°C
Short Circuit Output Current	100 mA

*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

(VCC = 3.3V -5% / +10% UNLESS OTHERWISE NOTED; 0°C £ TA £ 70°C,

COMMERCIAL; -40°C£TA £85°C, INDUSTRIAL)

Parameter	Symbol	Min	Max	Units
Supply Voltage (1)	VCC	3.135	3.6	V
Input High Voltage (1,2)	VIH	2.0	VCC +0.3	V
Input Low Voltage (1,2)	VIL	-0.3	0.8	V
Input Leakage Current	ILI	-10	10	µA
0 £ VIN £ VCC
Output Leakage (Output Disabled)	ILO	-10	10	µA
0 £ VIN £ VCC
SSRAM Output High (IOH = -4mA) (1)	VOH	2.4	—	V
SSRAM Output Low (IOL = 8mA) (1)	VOL	—	0.4	V
SDRAM Output High (IOH = -2mA)	VOH	2.4	—	V
SDRAM Output Low (IOL = 2mA)	VOL	—	0.4	V

NOTES:

1.All voltages referenced to VSS (GND).

2.Overshoot: VIH £ +6.0V for t £ tKC/2 Underershoot: VIL ³ -2.0V for t £ tKC/2

DC ELECTRICAL CHARACTERISTICS

(VCC = 3.3V -5% / +10% UNLESS OTHERWISE NOTED; 0°C £TA £70°C, COMMERCIAL; -40°C £TA £85°C, INDUSTRIAL)

Description

Conditions

Symbol

Frequency

Typ

Max

Units

133MHz

500

625

Power Supply Current:

SSRAM Active / DRAM Auto Refresh

ICC1

150MHz

500

650

Operating (1,2,3)

166MHz

550

700

mA

200MHz

600

800

133MHz

325

425

Power Supply Current

SSRAM Active / DRAM Idle

ICC2

150MHz

350

450

Operating (1,2,3)

166MHz

400

495

mA

200MHz

450

585

Power Supply Current

83MHz

500

625

SSRAM Active / SSRAM Idle

ICC3

100MHz

500

650

mA

Operating (1,2,3)

125MHz

550

700

SSCE and SDCE £ VCC -0.2V,

CMOS Standby

All other inputs at VSS +0.2 £ VIN or

ISB1

20.0

40.0

mA

VIN £ VCC -0.2V, Clk frequency = 0

SSCE and SDCE £ VIH min

TTL Standby

All other inputs at VIL max £ VIN or

ISB2

30.0

55.0

mA

VIN £ VCC -0.2V, Clk frequency = 0

Auto Refresh

ICC5

250

300

mA

NOTES:

1.ICC (operating) is specified with no output current. ICC (operating) increases with faster cycle times and greater output loading.

2."Device idle" means device is deselected (CE = VIH) Clock is running at max frequency and Addresses are switching each cycle.

3.Typical values are measured at 3.3V, 25°C. ICC (operating) is specified at specified frequency.

BGACAPACITANCE

Description	Conditions	Symbol	Typ	Max	Units
Address Input Capacitance (1)	TA = 25°C; f = 1MHz	CI	5	8	pF
Input/Output Capacitance (DQ) (1)	TA = 25°C; f = 1MHz	CO	8	10	pF
Control Input Capacitance (1)	TA = 25°C; f = 1MHz	CA	5	8	pF
Clock Input Capacitance (1)	TA = 25°C; f = 1MHz	CCK	4	6	pF

NOTE:

1. This parameter is sampled.

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White Electronic Designs								WED9LC6816V
	SSRAM AC CHARACTERISTICS
(VCC = 3.3V -5% / +10% UNLESS OTHERWISE NOTED; 0°C £ TA £ 70°C, COMMERCIAL; -40°C £ TA £ 85°C, INDUSTRIAL)
	Symbol	200MHz			166MHz		150MHz			133MHz
Parameter		Min	Max		Min	Max	Min		Max	Min	Max	Units
Clock Cycle Time	tKHKH	5			6		7			8		ns
Clock HIGH Time	tKLKH	1.6			2.4		2.6			2.8		ns
Clock LOW Time	tKHKL	1.6			2.4		2.6			2.8		ns
Clock to output valid	tKHQV		2.5			3.5			3.8		4.0	ns
Clock to output invalid	tKHQX	1.5			1.5		1.5			1.5		ns
Clock to output on Low-Z	tKQLZ	0			0		0			0		ns
Clock to output in High-Z	tKQHZ	1.5	3		1.5	3.5	1.5		3.8	1.5	4.0	ns
Output Enable to output valid	tOELQV		2.5			3.5			3.8		4.0	ns
Output Enable to output in Low-Z	tOELZ	0			0		0			0		ns
Output Enable to output in High-Z	tOEHZ		3.0			3.5			3.5		3.8	ns
Address, Control, Data-in Setup Time to Clock	t S	1.5			1.5		1.5			1.5		ns
Address, Control, Data-in Hold Time to Clock	tH	0.5			0.5		0.5			0.5		ns

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WED9LC6816V

SSRAM OPERATION TRUTH TABLE

Operation

Address Used

SSCE

SSADS

SSWE

SSOE

DQ

Deselected Cycle, Power Down

None

H

L

X

X

High-Z

WRITE Cycle, Begin Burst

External

L

L

L

X

D

READ Cycle, Begin Burst

External

L

L

H

L

Q

READ Cycle, Begin Burst

External

L

L

H

H

High-Z

READ Cycle, Suspend Burst

Current

X

H

H

L

Q

READ Cycle, Suspend Burst

Current

X

H

H

H

High-Z

READ Cycle, Suspend Burst

Current

H

H

H

L

Q

READ Cycle, Suspend Burst

Current

H

H

H

H

High-Z

WRITE Cycle, Suspend Burst

Current

X

H

L

X

D

WRITE Cycle, Suspend Burst

Current

H

H

L

X

D

NOTE:

1.X means “don’t care”, H means logic HIGH. L means logic LOW.

2.All inputs except SSOE must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLK.

3.Suspending burst generates wait cycle

4.For a write operation following a read operation, SSOE must be HIGH before the input data required setup time plus High-Z time for SSOE and staying HIGH through out the input data hold time.

5.This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

SSRAM PARTIAL TRUTH TABLE

Function

0

1

2

3

SSWE

BWE

BWE

BWE

BWE

READ

H

X

X

X

X

WRITE one Byte (DQ0-7)

L

L

H

H

H

WRITE all Bytes

L

L

L

L

L

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White Electronic Designs					WED9LC6816V
FIG. 3 SSRAM READ TIMING
	tKHKH	tKHKL tKLKH
SSCLK
	tS			tH
SSADS
	tS
SSCE
					tH
	tS
ADDR	A1 A2	A3	A4	A5
	tH
SSOE
					tOEHZ
	tOELQV
SSWE
	tKQLZ	tKHQX	tKHQV
DQ		Q(A1)	Q(A2)	Q(A3)	Q(A4) Q(A5)

FIG. 4 SSRAM WRITE TIMING

tKHKH tKHKL tKLKH

SSCLK

tS					tH
SSADS
tH
SSCE
					tH
	tS
ADDR	A1	A2	A3	A4	A5
	tH
	tOEHZ
SSOE		Must be HIGH
	tS				KHGWX
					tH
SSWE
	tS	tH
DQ	D(A1)	D(A2)	D(A3)	D(A4)	D(A5)

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White Electronic Designs									WED9LC6816V
		SDRAM AC CHARACTERISTICS
(VCC = 3.3V -5% / +10% UNLESS OTHERWISE NOTED; 0°C£TA£70°C, COMMERCIAL; -40°C£TA£85°C, INDUSTRIAL)
			Symbol	125MHz				100MHz		83MHz
Parameter				Min			Max	Min	Max	Min	Max	Units
Clock Cycle Time (1)		CL = 3	tCC	8		1000		10	1000	12	1000	ns
		CL = 2	tCC	10		1000		12	1000	15	1000
Clock to valid Output delay (1,2)			tSAC			6			7		8	ns
Output Data Hold Time (2)			tOH	3				3		3		ns
Clock HIGH Pulse Width (3)			tCH	3				3		3		ns
Clock LOW Pulse Width (3)			tCL	3				3		3		ns
Input Setup Time (3)			tSS	2				2		2		ns
Input Hold Time (3)			tSH	1				1		1		ns
CLK to Output Low-Z (2)			tSLZ	2				2		2		ns
CLK to Output High-Z			tSHZ			7			7		8	ns
Row Active to Row Active Delay (4)			tRRD	20				20		24		ns
RAS\ to CAS\ Delay (4)			tRCD	20				20		24		ns
Row Precharge Time (4)			tRP	20				20		24		ns
Row Active Time (4)			tRAS	50		10,000		50	10,000	60	10,000	ns
Row Cycle Time - Operation (4)			tRC	70				80		90		ns
Row Cycle Time - Auto Refresh (4,8)			tRFC	70				80		90		ns
Last Data in to New Column Address Delay (5)			tCDL	1				1		1		CLK
Last Data in to Row Precharge (5)			tRDL	1				1		1		CLK
Last Data in to Burst Stop (5)			tBDL	1				1		1		CLK
Column Address to Column Address Delay (6)			tCCD	1.5				1.5		1.5		CLK
Number of Valid Output Data (7)				2				2		2		ea
				1				2		1

NOTES:

1.Parameters depend on programmed CAS latency.

2.If clock rise time is longer than 1ns (trise/2 -0.5)ns should be added to the parameter.

3.Assumed input rise and fall time = 1ns. If trise of tfall are longer than 1ns. [(trise = tfall)/2] - 1ns should be added to the parameter.

4.The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer.

5.Minimum delay is required to complete write.

6.All devices allow every cycle column address changes.

7.In case of row precharge interrupt, auto precharge and read burst stop.

8.A new command may be given tRFC after self-refresh exit.

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	White Electronic Designs																WED9LC6816V
		CLOCK FREQUENCY AND LATENCY PARAMETERS - 125MHZ SDRAM
				(UNIT = NUMBER OF CLOCK)
Frequency		CAS		tRC		tRAS		tRP			tRRD		tRCD				tCCD		tCDL		tRDL
		Latency		70ns		50ns		20ns			20ns		20ns				10ns		10ns		10ns
125MHz (8.0ns)		3	9			6		3			2		3			1			1		1
100MHz (10.0ns)		3	7			5		2			2		2			1			1		1
83MHz (12.0ns)		2	6			4		2			2		2			1			1		1
		CLOCK FREQUENCY AND LATENCY PARAMETERS - 100MHZ SDRAM
				(UNIT = NUMBER OF CLOCK)
Frequency		CAS		tRC		tRAS		tRP			tRRD		tRCD				tCCD		tCDL		tRDL
		Latency		70ns		50ns		20ns			20ns		20ns				10ns		10ns		10ns
100MHz (12.0ns)		3	7			5		2			2		2				1		1		1
83MHz (12.0ns)		2	6			5		2			2		2				1		1		1
				REFRESH CYCLE PARAMETERS
								-10							-12
Parameter				Symbol				Min				Max			Min				Max		Units
Refresh Period (1,2)					tREF			—			64				—				64		ms

NOTES:

1.4096 cycles

2.Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device.

SDRAM COMMAND TRUTH TABLE

A12, A13

SDA10

Function

SDCE

SDRAS

SDCAS

SDWE

BWE

Notes

A11-0

Mode Register Set

L

L

L

L

X

OP CODE

Auto Refresh (CBR)

L

L

L

H

X

X

X

Precharge

Single Bank

L

L

H

L

X

BA

L

2

Precharge all Banks

L

L

H

L

X

X

H

Bank Activate

L

L

H

H

X

BA

Row Address

2

Write

L

H

L

L

X

BA

L

2

Write with Auto Precharge

L

H

L

L

X

BA

H

2

Read

L

H

L

L

X

BA

L

2

Read with Auto Precharge

L

H

L

H

X

BA

H

2

Burst Termination

L

H

H

L

X

X

X

3

No Operation

L

H

H

H

X

X

X

Device Deselect

H

X

X

X

X

X

X

Data Write/Output Disable

X

X

X

X

L

X

X

4

Data Mask/Output Disable

X

X

X

X

H

X

X

4

NOTES:

1.All of the SDRAM operations are defined by states of SDCE\, SDWE\, SDRAS\, SDCAS\, and BWE0-3 at the positive rising edge of the clock.

2.Bank Select (BA), A12 (BA0) and A13 (BA1) select between different banks.

3.During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.

4.The BWE has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. BWE also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency).

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