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WE512K16-XG4X |
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HI-RELIABILITY PRODUCT |
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512Kx16 CMOS EEPROM MODULE |
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FEATURES |
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■ Access Time of 140, 150, 200ns |
■ Automatic Page Write Operation |
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■ Packaging: |
■ Page Write Cycle Time: 10ms Max |
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• 68 lead, 40mm Hermetic CQFP (Package 501) |
■ Data Polling for End of Write Detection |
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■ Organized as 4 banks of 128Kx16 |
■ Hardware and Software Data Protection |
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■ Write Endurance 10,000 Cycles |
■ TTL Compatible Inputs and Outputs |
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■ Data Retention Ten Years Minimum |
■ 5 Volt Power Supply |
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■ Military Temperature Range |
■ 8 Built-in Decoupling Caps and Multiple Ground Pins for Low |
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■ Low Power CMOS |
Noise Operation |
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■ Weight - 20 grams typical |
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FIG. 1 PIN CONFIGURATION |
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TOP VIEW
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NC |
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A0 |
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A1 |
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A2 |
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A3 |
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A4 |
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A5 |
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CS1 |
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GND |
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CS3 |
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WE A6 |
A7 |
A8 |
A9 |
A10 |
VCC |
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9 |
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8 |
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7 |
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6 |
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5 |
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4 |
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3 |
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2 |
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1 |
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68 67 66 65 64 63 62 61 |
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I/O0 |
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10 |
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60 |
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NC |
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I/O1 |
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11 |
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59 |
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NC |
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I/O2 |
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12 |
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58 |
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INC |
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I/O3 |
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13 |
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57 |
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NC |
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I/O4 |
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14 |
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56 |
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NC |
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I/O5 |
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15 |
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55 |
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NC |
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I/O6 |
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16 |
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54 |
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NC |
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I/O7 |
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17 |
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53 |
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NC |
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GND |
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18 |
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52 |
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GND |
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I/O8 |
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19 |
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51 |
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NC |
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I/O9 |
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20 |
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50 |
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NC |
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I/O10 |
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21 |
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49 |
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NC |
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I/O11 |
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22 |
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48 |
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NC |
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I/O12 |
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23 |
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47 |
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NC |
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I/O13 |
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24 |
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46 |
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NC |
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I/O14 |
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25 |
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45 |
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NC |
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I/O15 |
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26 |
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44 |
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NC |
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27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 |
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VCC |
A11 |
A12 |
A13 |
A14 |
A15 |
A16 |
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CS2 |
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OE |
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CS4 |
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NC NC |
NC |
NC |
NC |
NC |
NC |
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PIN DESCRIPTION
I/O0-15 |
Data Inputs/Outputs |
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A0-16 |
Address Inputs |
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Write Enable |
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WE |
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1-4 |
Chip Selects |
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CS |
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Output Enable |
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OE |
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VCC |
Power Supply |
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GND |
Ground |
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NC |
Not Connected |
BLOCK DIAGRAM |
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CS1 CS 2 CS3 CS4 |
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A 0 - 16 |
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OE |
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WE |
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128K x 8 |
128K x 8 |
128K x 8 |
128K x 8 |
128K x 8 |
128K x 8 |
128K x 8 |
128K x 8 |
I/O 0 - 7 |
I/O 8 - 1 5 |
NOTE:
CS1-4 are used as bank selects. During reads, only one CSx can be active at one time.
April 1999 Rev. 2 |
1 |
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 |
WE512K16-XG4X
ABSOLUTE MAXIMUM RATINGS
Parameter |
Symbol |
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Unit |
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Operating Temperature |
TA |
-55 to +125 |
°C |
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Storage Temperature |
TSTG |
-65 to +150 |
°C |
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Signal Voltage Relative to GND |
VG |
-0.6 to +6.25 |
V |
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Voltage on |
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and A9 |
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-0.6 to +13.5 |
V |
OE |
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NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter |
Symbol |
Min |
Max |
Unit |
Supply Voltage |
VCC |
4.5 |
5.5 |
V |
Input High Voltage |
VIH |
2.0 |
Vcc + 0.3 |
V |
Input Low Voltage |
VIL |
-0.3 |
+0.8 |
V |
Operating Temp. (Mil.) |
TA |
-55 |
+125 |
°C |
TRUTH TABLE
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CS |
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OE |
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WE |
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Mode |
Data I/O |
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H |
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X |
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X |
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Standby |
High Z |
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L |
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L |
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H |
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Read |
Data Out |
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L |
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H |
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L |
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Write |
Data In |
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X |
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H |
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X |
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Out Disable |
High Z/Data Out |
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X |
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X |
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H |
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Write |
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X |
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L |
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X |
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Inhibit |
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CAPACITANCE
(TA = +25°C)
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Parameter |
Symbol |
Conditions |
Max |
Unit |
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capacitance |
COE |
VIN = 0 V, f = 1.0 MHz |
50 |
pF |
|
OE |
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|
capacitance |
CWE |
VIN = 0 V, f = 1.0 MHz |
50 |
pF |
|
WE |
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CS1-4 capacitance |
CCS |
VIN = 0 V, f = 1.0 MHz |
25 |
pF |
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Data I/O capacitance |
CI/O |
VI/O = 0 V, f = 1.0 MHz |
40 |
pF |
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Address input capacitance |
CAD |
VIN = 0 V, f = 1.0 MHz |
70 |
pF |
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)
Parameter |
Symbol |
|
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|
Conditions |
Min |
Max |
Unit |
Input Leakage Current |
ILI |
VCC = 5.5, VIN = GND to VCC |
|
10 |
µA |
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Output Leakage Current |
ILO |
|
|
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|
|
= VIH, |
|
|
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|
|
= VIH, VOUT = GND to VCC |
|
10 |
µA |
|||
CS |
OE |
|
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Operating Supply Current (x16) |
ICCx16 |
|
|
|
|
1 = VIL, |
|
|
|
= |
|
2-4 = VIH, f = 5MHz, VCC = 5.5 |
|
160 |
mA |
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|
CS |
|
OE |
CS |
|
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Chip Erase Current |
ICC1 |
|
|
= VIL, |
|
|
|
= VIH, f = 5MHz, VCC = 5.5 |
|
250 |
mA |
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CS |
OE |
|
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Standby Current (CMOS) |
ISB |
|
|
= VIH, |
|
= VIH, f = 5MHz, VCC = 5.5 |
|
5 |
mA |
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|
CS |
OE |
|
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Output Low Voltage |
VOL |
IOL = 2.1mA, VCC = 4.5V |
|
0.45 |
V |
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Output High Voltage |
VOH |
IOH = -400µA, VCC = 4.5V |
2.4 |
|
V |
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
FIG. 2
AC TEST CIRCUIT
I OL
Current Source
D.U.T. |
VZ ≈1.5V |
Ceff = 50 pf |
(Bipolar Supply) |
|
IOH
Current Source
AC TEST CONDITIONS
Parameter |
Typ |
Unit |
Input Pulse Levels |
VIL = 0, VIH = 3.0 |
V |
|
|
|
Input Rise and Fall |
5 |
ns |
|
|
|
Input and Output Reference Level |
1.5 |
V |
|
|
|
Output Timing Reference Level |
1.5 |
V |
|
|
|
NOTES:
VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 |
2 |
WRITE
A write cycle is initiated when OE is high and a low pulse is on WE or CS with CS or WE low. The address is latched on the falling edge of CS or WE whichever occurs last. The data is latched by the rising edge of CS or WE, whichever occurs first. A word write operation will automatically continue to completion.
WRITE CYCLE TIMING
Figures 3 and 4 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the CS line low. Write enable consists of setting the WE line low. The write cycle begins when the last of either CS or WE goes low.
The WE line transition from high to low also initiates an internal 150 sec delay timer to permit page mode operation. Each subsequent WE transition from high to low that occurs before the completion of the 150 sec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot.
WE512K16-XG4X
AC WRITE CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)
Write Cycle Parameter |
Symbol |
Min |
Max |
Unit |
||||
Write Cycle Time, TYP = 6ms |
tWC |
|
10 |
ms |
||||
Address Set-up Time |
tAS |
10 |
|
ns |
||||
|
|
|
|
|
|
|
||
Write Pulse Width |
(WE |
or |
CS) |
|
tWP |
120 |
|
ns |
Chip Select Set-up Time |
tCS |
0 |
|
ns |
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Address Hold Time |
tAH |
100 |
|
ns |
||||
Data Hold Time |
tDH |
10 |
|
ns |
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Chip Select Hold Time |
tCSH |
0 |
|
ns |
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Data Set-up Time |
tDS |
100 |
|
ns |
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Output Enable Set-up Time |
tOES |
10 |
|
ns |
||||
Output Enable Hold Time |
tOEH |
10 |
|
ns |
||||
Write Pulse Width High |
tWPH |
50 |
|
ns |
3 |
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 |