White Electronic Designs EDI8L32128C25AC, EDI8L32128C20AI, EDI8L32128C20AC, EDI8L32128C17AI, EDI8L32128C17AC Datasheet

White Electronic Designs

EDI8L32128C

128Kx32 CMOS High Speed Static RAM

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DESCRIPTION

FEATURES

ν

128Kx32Obit CMOS Static

The EDI8L32128C is a high speed, high performance,

T

four megabit density Static RAM organized as a

ν Random Access Memory Array

128Kx32 bit array.

•

Fast Access Times: 12, 15, 17, 20, and 25ns

Four Chip Enables, Write Control, and Output Enable

•

Individual Byte Enables

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provide the user with a flexible memory solution. The

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User Configurable Organization with Minimal

user may independently enable each of the four bytes,

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and, with minimal additional peripheral logic, the unit

Additional Logic

•

Master Output EnableCand Write Control

may be configured as a 256Kx16 or 512Kx8 array.

•

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Fully asynchronous circuitry is used, requiring no clocks

TTL Compatible Inputs and Outputs

or refreshing for operation and providing equal access

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Fully Static, No Clocks

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and cycle times for ease of use.

ν

Surface Mount Package

The EDI8L32128C, allows 4 megabits of memory to

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be placed in less than 0.990 square inches of board

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68 Lead PLCC, No. 99 (JEDEC MO-47AE)

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Small Footprint, 0.990 Sq. In.

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space; a savings of 0.885 square inches over four

standard 128Kx8 components.

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Multiple Ground Pins for Maximum Noise

Immunity

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NOTE: Solder Reflow temperature should not exceed 230°C

D

ν Single +5V (±5%) Supply Operation

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FIG. 1 PIN CONFIGURATION

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TOP VIEW

PIN DESCRIPTION

F

AØ-16

Address Inputs

Ø-3

Chip Enables (One per Byte)

O

E

Master Write Enable

W

Master Output Enable

G

RDQØ-31

Common Data Input/Output

VCC

Power (+5V±5%)

VSS

Ground

NNC

No Connection

E

W

BLOCK DIAGRAM

D

E

S

IG

NOTE:Pin 2 & 67 on the 64Kx32 (EDI8L3265C) and the 256Kx32 (EDI8L32256C) are word select pins.

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August 2002 Rev. 6

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White Electronic Designs Corporation • [phone] • www.whiteedc.com

ECO #15423

White Electronic Designs

EDI8L32128C

ABSOLUTE MAXIMUM RATINGS*

Voltage on any pin relative to VSS	-0.5V to 7.0V
Operating Temperature TA (Ambient)
Commercial	0°C to + 70°C
Industrial	-40°C to +85°C
Storage Temperature	-55°C to +125°C
Power Dissipation	4 Watts
Output Current.	20 mA
Junction Temperature, TJ	175°C

*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

TRUTH TABLE

E	W	G	Mode	Output	Power
H	X	X	Standby	High Z	ICC2,ICC3,
L	H	H	Output Disable	High Z	ICC1
L	X	X	Output Disable	High Z	ICC1
L	H	L	Read	DOUT	ICC1
L	L	X	Write	DIN	ICC1

RECOMMENDED DC OPERATING CONDITIONS

Parameter	Sym	Min	Typ	Max	Units
Supply Voltage	VCC	4.75	5.0	5.25	V
Supply Voltage	VSS	0	0	0	V
Input High Voltage	VIH	2.2	--	VCC+0.5	V
Input Low Voltage	VIL	-0.3	--	0.8	V

CAPACITANCE

(f = 1.0MHz, VIN = VCC or VSS)

Parameter		Sym						Max	Unit
Address Lines			CA					40	pF
Data Lines		CD/Q						10	pF
Write & Output Enable Lines								40	pF
		W,				G
Chip Enable Lines/Byte Select				0-3				8	pF
			E

DC ELECTRICAL CHARACTERISTICS

Parameter

Sym

Conditions

Typ

Max

Units

12*

15

17

20/25

Operating Power Supply Current

ICC1

W= VIL, II/O = 0mA,

620

720

680

640

600

mA

Min Cycle

Standby (TTL) Supply Current

ICC2

E ž VIH, VIN - VIL or

160

160

160

160

mA

VIN ž VIH, f = ØMHz

Full Standby CMOS Supply Current

ICC3

E ž VCC -0.2V

VIN ž VCC -0.2V or

20

20

20

20

mA

VIN - 0.2V

Input Leakage Current

ILI

VIN = 0V to VCC

±10

µA

Output Leakage Current

ILO

V I/O = 0V to VCC

±10

µA

Output High Volltage

VOH

IOH = -4.0mA

2.4

V

Output Low Voltage

VOL

IOL = 8.0mA

0.4

V

Typical: TA = 25°C, VCC = 5.0V

AC TEST CONDITIONS

Input Pulse Levels	VSS to 3.0V
Input Rise and Fall Times	5ns
Input and Output Timing Levels	1.5V
Output Load	Figure 2

NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 3)

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