UCC3580Q-4
Texas Instruments UCC3580Q-4, UCC3580Q-3, UCC3580N-4, UCC3580N-3, UCC3580N-2 Datasheet
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UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
SLUS292 - FEBRUARY 1999
FEATURES
• Provides Auxiliary Switch Activation
Complementary to Main Power
Switch Drive
• Programmable deadtime (Turn-on
Delay) Between Activation of Each
Switch
• Voltage Mode Control with
Feedforward Operation
• Programmable Limits for Both
Transformer Volt- Second Product
and PWM Duty Cycle
• High Current Gate Driver for Both
Main and Auxiliary Outputs
• Multiple Protection Features with
Latched Shutdown and Soft Restart
• Low Supply Current (100µA Startup,
1.5mA Operation)
BLOCK DIAGRAM
DESCRIPTION
The UCC3580 family of PWM controllers is designed to implement a variety
of active clamp/reset and synchronous rectifier switching converter topolo-
gies. While containing all the necessary functions for fixed frequency, high
performance pulse width modulation, the additional feature of this design is
the inclusion of an auxiliary switch driver which complements the main
power switch, and with a programmable deadtime or delay between each
transition. The active clamp/reset technique allows operation of single
ended converters beyond 50% duty cycle while reducing voltage stresses
on the switches, and allows a greater flux swing for the power transformer.
This approach also allows a reduction in switching losses by recovering en-
ergy stored in parasitic elements such as leakage inductance and switch
capacitance.
The oscillator is programmed with two resistors and a capacitor to set
switching frequency and maximum duty cycle. A separate synchronized
ramp provides a voltage feedforward pulse width modulation and a pro-
grammed maximum volt-second limit. The generated clock from the oscilla-
tor contains both frequency and maximum duty cycle information.
(continued)
Single Ended Active Clamp/Reset PWM
UDG-95069-2
Pin Numbers refer to DIL-16 and SOIC-16 packages
2
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V
I
VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
LINE, RAMP . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to VDD + 1V
I
LINE
, I
RAMP
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3V
I
DELAY
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5mA
I
OUT1
(tpw < 1µs and Duty Cycle < 10%). . . . . . . −0.6A to 1.2A
I
OUT2
(tpw < 1µs and Duty Cycle < 10%). . . . . . . −0.4A to 0.4A
I
CLK
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −100mA to 100mA
OSC1, OSC2, SS, SHTDWN, EAIN . . . . . −0.3V to REF + 0.3V
I
EAOUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5mA to 5mA
I
REF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30mA
PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2V to 0.2V
Storage Temperature . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . −55°C to +150°C
Lead Temperature (Soldering, 10 sec.). . . . . . . . . . . . . +300°C
All voltages are with respect to ground unless otherwise stated.
Currents are positive into, negative out of the specified termi-
nal. Consult Packaging Section of Databook for thermal limita-
tions and considerations of packages.
ABSOLUTE MAXIMUM RATINGS
PLCC-20 (Top View)
Q Packages
CONNECTION DIAGRAMS
DIL-16, SOIC-16 (Top View)
J, N, or D Packages
ORDER INFORMATION
The main gate drive output (OUT1) is controlled by the
pulse width modulator. The second output (OUT2) is in-
tended to activate an auxiliary switch during the off time
of the main switch, except that between each transition
there is deadtime where both switches are off, pro-
grammed by a single external resistor. This design offers
two options for OUT2, normal and inverted. In the -1 and
-2 versions, OUT2 is normal and can be used to drive
PMOS FETs. In the -3 and -4 versions, OUT2 is inverted
and can be used to drive NMOS FETs. In all versions,
both the main and auxiliary switches are held off prior to
startup and when the PWM command goes to zero duty
cycle. During fault conditions, OUT1 is held off while
OUT2 operates at maximum duty cycle with a guaran-
teed off time equal to the sum of the two deadtimes.
Undervoltage lockout monitors supply voltage (VDD), the
precision reference (REF), input line voltage (LINE), and
the shutdown comparator (SHTDWN). If after any of
these four have sensed a fault condition, recovery to full
operation is initiated with a soft start. VDD thresholds, on
and off, are 15V and 8.5V for the -2 and -4 versions, 9V
and 8.5V for the -1 and -3 versions.
The UCC1580-x is specified for operation over the mili-
tary temperature range of −55°C to 125°C. The
UCC2580-x is specified from −40°C to 85°C. The
UCC3580-x is specified from 0°C to 70°C. Package op-
tions include 16-pin surface mount or dual in-line, and
20-pin plastic leadless chip carrier.
DESCRIPTION (cont.)
3
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, all specifications are over the full temperature range, VDD
= 12V, R1 = 18.2k, R2 = 4.41k, C
T
= 100pF, R3 = 100k, C
OUT1
= 0, C
OUT2
= 0. T
A
= 0°C to 70°C for the UCC3580, −40°C to 85°C
for the UCC2580, −55°C to 125°C for the UCC1580, T
A
= T
J
.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Oscillator Section
Frequency 370 400 430 kHz
CLK Pulse Width 650 750 850 ns
CLK V
OH
I
CLK
= −3mA 4.3 4.7 V
CLK V
OL
I
CLK
= 3mA 0.3 0.5 V
Ramp Generator Section
Ramp V
OL
I
RAMP
= 100µA 50 100 mV
Flux Comparator Vth 3.16 3.33 3.50 V
Pulse Width Modulator Section
Minimum Duty Cycle OUT1, EAOUT = VOL 0 %
Maximum Duty Cycle OUT1, EAIN = 2.6V 63 66 69 %
PWM Comparator Offset 0.1 0.4 0.9 V
Error Amplifier Section
EAIN EAOUT = EAIN 2.44 2.5 2.56 V
I
EAIN
EAOUT = EAIN 150 400 nA
EAOUT, VOL EAIN = 2.6V, I
EAOUT
= 100µA 0.3 0.5 V
EAOUT, VOH EAIN = 2.4V, I
EAOUT
= −100µA 4 5 5.5 V
AVOL 70 80 dB
Gain Bandwidth Product f = 100kHz (Note 1) 2 6 MHz
Softstart/Shutdown Section
Start Duty Cycle EAIN = 2.4V 0 %
SS V
OL I
SS
= 100µA 100 350 mV
SS Restart Threshold 400 550 mV
I
SS
–20 –35 µA
SHTDWN V
TH
0.4 0.5 0.6 V
I
SHTDWN
50 150 nA
Undervoltage Lockout Section
VDD On UCC3580-2,-4 14 15 16 V
UCC3580-1,-3 8 9 10 V
VDD Off 7.5 8.5 9.5 V
LINE On 4.7 5 5.3 V
LINE Off 4.2 4.5 4.8 V
I
LINE
LINE = 6V 50 150 nA
Supply Section
VDD Clamp I
VDD
= 10mA 14 15 16 V
I
VDD
Start VDD < VDD On 160 250 µA
I
VDD
Operating No Load 2.5 3.5 mA
Output Drivers Section
OUT1 V
SAT
High I
OUT1
= −50mA 0.4 1.0 V
OUT1 V
SAT
Low I
OUT1
=100mA 0.4 1.0 V
OUT2 V
SAT
High I
OUT2
= −30mA 0.4 1.0 V
OUT2 V
SAT
Low I
OUT2
= 30mA 0.4 1.0 V
OUT1 Fall Time C
OUT1
= 1nF, RS = 3Ω 20 50 ns
OUT1 Rise Time C
OUT1
= 1nF, RS = 3Ω 40 80 ns
OUT2 Fall Time C
OUT2
= 300pF, RS = 10Ω 20 50 ns
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