Texas Instruments UCC3809PW-1, UCC3809P-1, UCC3809N-2, UCC3809N-1, UCC3809DTR-2 Datasheet

application

INFO

available

UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2

Economy Primary Side Controller

FEATURES

•User Programmable Soft Start With Active Low Shutdown

•User Programmable Maximum Duty Cycle

•Accessible 5V Reference

•Undervoltage Lockout

•Operation to 1MHz

•0.4A Source/0.8A Sink FET Driver

•Low 100 A Startup Current

PART	TURN ON	TURN OFF
NUMBER	THRESHOLD	THRESHOLD
UCCX809-1	10V	8V
UCCX809-2	15V	8V

DESCRIPTION

The UCC3809 family of BCDMOS economy low power integrated circuits contains all the control and drive circuitry required for off-line and isolated DC-to-DC fixed frequency current mode switching power supplies with minimal external parts count. Internally implemented circuits include undervoltage lockout featuring startup current less than 100 A, a user accessible voltage reference, logic to ensure latched operation, a PWM comparator, and a totem pole output stage to sink or source peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the off state.

Oscillator frequency and maximum duty cycle are programmed with two resistors and a capacitor. The UCC3809 family also features full cycle soft start.

The family has UVLO thresholds and hysteresis levels for off-line and DC-to-DC systems as shown in the table to the left.

The UCC3809 and the UCC2809 are offered in the 8 pin SOIC (D), PDIP (N), TSSOP (PW), and MSOP (P) packages. The small TSSOP and MSOP packages make the device ideal for applications where board space and height are at a premium.

TYPICAL APPLICATION DIAGRAM

VIN	RSTART
		FB	1V
			1
		NOISE	1V				REF
						5V
		FILTER	+5V				8
						REF
FEEDBACK
		SS	6 A				CREF
			2				VOUT
CURRENT	SLOPE		0.5V
SENSE	COMP	CSS					VDD
							7
		DISABLE				15/8V
						10/8V
					UVLO
						17.5V	CVDD
		RT1			PWM
			3		LATCH
							OUT
				CLK	R
			OSC		Q		6
		RT2
					S
			4				GND
							VREF
		CT					5
							UDG-99036
SLUS166A - NOVEMBER 1999

ABSOLUTE MAXIMUM RATINGS*

VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19V

IVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA IOUT (tpw < 1 s and Duty Cycle < 10%). . . . . . . . –0.4A to 0.8A RT1, RT2, SS . . . . . . . . . . . . . . . . . . . . . . –0.3V to REF + 0.3V

IREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15mA Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C

* Values beyond which damage may occur.

All voltages are with respect to ground unless otherwise stated. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.

TSSOP-8 (Top View)
PW Package
1	FB	REF	8
2	SS	VDD	7
3	RT1	OUT	6
4	RT2	GND	5

UCC1809-1/-2

UCC2809-1/-2

UCC3809-1/-2

CONNECTION DIAGRAM

SOIC-8, DIL-8 (Top View)

D, N and J Packages

MSOP-8 (Top View)

P Package

	1		FB	REF		8
	2		SS	VDD		7
	3		RT1	OUT		6
				GND
	4		RT2			5

			ORDERING INFORMATION
	Temperature Range	Available Packages	UCC 809 –
UCC1809-X	–55°C to +125°C	J
UCC2809-X	–40°C to +85°C	N, D, P, PW
UCC3809-X	0°C to +70°C	N, D, P, PW

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD = 12V. TA = TJ.

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Supply Section
VDD Clamp	IVDD = 10mA	16	17.5	19	V
IVDD	No Load		600	900	A
IVDD Starting				100	A
Undervoltage Lockout Section
Start Threshold (UCCx809-1)		9.4		10.4	V
UVLO Hysteresis (UCCx809-1)		1.65			V
Start Threshold (UCCx809-2)		14.0		15.6	V
UVLO Hysteresis (UCCx809-2)		6.2			V
Voltage Reference Section
Output Voltage	IREF = 0mA	4.75	5	5.25	V
Line Regulation	VDD = 10V to 15V		2		mV
Load Regulation	IREF = 0mA to 5mA		2		mV
Comparator Section
IFB	Output Off		–100		nA
Comparator Threshold		0.9	0.95	1	V
OUT Propagation Delay (No Load)	VFB = 0.8V to 1.2V at TR = 10ns		50	100	ns

2

UCC1809-1/-2

UCC2809-1/-2

UCC3809-1/-2

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD = 12V. TA = TJ.

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Soft Start Section
ISS		VDD = 16V, VSS = 0V; –40°C to +85°C	–4.9	–7.0	–9.1	A
		VDD = 16V, VSS = 0V; < –40°C; >+85°C	–4.0	–7.0	–10.0	A
VSS Low		VDD = 7.5V, ISS = 200 A			0.2	V
Shutdown Threshold			0.44	0.48	0.52	V
Oscillator Section
Frequency		RT1 = 10k, RT2 = 4.32k, CT = 820pF	90	100	110	kHz
Frequency Change with Voltage		VDD = 10V to 15V		0.1		%/V
CT Peak Voltage				3.33		V
CT	Valley Voltage			1.67		V
CT	Peak to Peak Voltage		1.54	1.67	1.80	V
Output Section
Output VSAT Low		IOUT = 80mA (dc)		0.8	1.5	V
Output VSAT High		IOUT = –40mA (dc), VDD – OUT		0.8	1.5	V
Output Low Voltage During UVLO		IOUT = 20mA (dc)			1.5	V
Minimum Duty Cycle		VFB = 2V		0		%
Maximum Duty Cycle				70		%
Rise Time		COUT = 1nF		35		ns
Fall Time		COUT = 1nF		18		ns

PIN DESCRIPTIONS

FB: This pin is the summing node for current sense feedback, voltage sense feedback (by optocoupler) and slope compensation. Slope compensation is derived from the rising voltage at the timing capacitor and can be buffered with an external small signal NPN transistor. External high frequency filter capacitance applied from this node to GND is discharged by an internal 250Ω on resistance NMOS FET during PWM off time and offers effective leading edge blanking set by the RC time constant of the feedback resistance from current sense resistor to FB input and the high frequency filter capacitor capacitance at this node to GND.

GND: Reference ground and power ground for all functions.

OUT: This pin is the high current power driver output. A minimum series gate resistor of 3.9 is recommended to limit the gate drive current when operating with high bias voltages.

REF: The internal 5V reference output. This reference is buffered and is available on the REF pin. REF should be bypassed with a 0.47µF ceramic capacitor.

RT1: This pin connects to timing resistor RT1 and controls the positive ramp time of the internal oscillator (Tr = 0.74 • (CT + 27pF) • RT1). The positive threshold of the internal oscillator is sensed through inactive timing resistor RT2 which connects to pin RT2 and timing capacitor CT.

RT2: This pin connects to timing resistor RT2 and controls the negative ramp time of the internal oscillator (Tf = 0.74 • (CT + 27pF) • RT2). The negative threshold of the internal oscillator is sensed through inactive timing resistor RT1 which connects to pin RT1 and timing capacitor CT.

SS: This pin serves two functions. The soft start timing capacitor connects to SS and is charged by an internal 6µA current source. Under normal soft start SS is discharged to at least 0.4V and then ramps positive to 1V during which time the output driver is held low. As SS charges from 1V to 2V soft start is implemented by an increasing output duty cycle. If SS is taken below 0.5V, the output driver is inhibited and held low. The user accessible 5V voltage reference also goes low and IVDD < 100µA.

VDD: The power input connection for this device. This pin is shunt regulated at 17.5V which is sufficiently below the voltage rating of the DMOS output driver stage. VDD should be bypassed with a 1µF ceramic capacitor.

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