Texas Instruments UCC3752N, UCC3752DTR, UCC3752D, UCC2752N, UCC2752DTR Datasheet
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Resonant Ring Generator Controller
UCC2752
UCC3752
PRELIMINARY
FEATURES
•Novel Topology for Low-Cost, Efficient Generation of Ring Voltage
•Suitable for Multi-Line Operation
•Selectable 20, 25 and 50 Hz Ring Frequency
•Secondary (AC) Current Limiting Generates an Off-Hook Detect Signal
•Primary Current Limiting to Turn Power Stage Off Under Fault Conditions
•Operates from a Single 12V Supply
DESCRIPTION
The UCC3752 controller is designed for driving a power stage that generates low frequency, high voltage sinusoidal signals for telephone ringing applications. The controller and the power stage are most suitable for up to 5 line applications where low cost, high efficiency and minimum parts count are critical. A semi-regulated DC voltage is added as an offset to the ringing signal. The ring generator operation is non-isolated and open loop.
The UCC3752 directly drives primary side switches used to implement a push-pull resonant converter topology and transformer coupled sampling switches located on the secondary of the converter. For normal ring signal generation, the primary switching frequency and secondary sampling frequency are precisely offset from each other by the ringing frequency to produce a high voltage low frequency alias signal at the output. The off-hook condition is detected by sensing the AC current and when AC limit is exceeded, a flag is generated on the OFFHOOK pin.
The drive signal frequencies are derived from a high frequency (3579545 Hz) crystal. The primary switching frequency is 89.489 kHz and the sampling frequency is 20, 25 or 50 Hz less depending on the status of frequency select pins FS0 and FS1.
The circuits described in this datasheet are covered under US Patent #5,663,878 and other patents pending.
TYPICAL APPLICATION |
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D1 |
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RSENSE |
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LIN |
T1 |
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CDC |
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DC SIGNAL |
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VIN |
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12V |
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V1 |
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LR |
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CR2 |
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AC SIGNAL |
CF |
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SAMPLING |
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VOUT |
LR |
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CIRCUIT |
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12V |
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N:1 |
CBYP1 |
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9 |
12 |
2 |
6 |
4 |
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CBYP2 |
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CR1 |
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VS12 |
DRVS |
N/C |
OHD |
VDD |
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Q1 |
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11 |
DRV1 |
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5 |
DCLIM |
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UCC3752 |
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ENABLE |
10 |
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OFFHOOK |
1 |
Q2 |
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13 |
DRV2 |
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XTAL2 |
15 |
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GND |
PGND |
FS0 |
FS1 |
XTAL1 |
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3 |
14 |
7 |
8 |
16 |
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3.579545MHz |
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UDG-98058
SLUS269 - JULY 1999
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2V Analog Inputs (OHD, DCLIM, XTAL1, XTAL2)
Maximum Forced Voltage. . . . . . . . . . . . . . . . . . . . –0.3 to 5V Logic Inputs
Maximum Forced Voltage . . . . . . . . . . . . . . . . . . –0.3 to 7.5V Reference Output Current (VDD) . . . . . . . . . . . Internally Limited Output Current (DRV1, DRV2, DRVS) Pulsed . . . . . . . . . . 1.5A Operating Junction Temperature . . . . . . . . . . –40°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Note: Unless otherwise indicated, voltages are referenced to ground and currents are positive into, negative out of, the specific terminals. Pulsed is defined as a less than 10% duty cycle with a maximum duration of 500
S.
Table I. Frequency selectability decoding.
FS1 |
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FS0 |
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MODE |
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Sine Wave |
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Frequency (Hz) |
0 |
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0 |
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1 |
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20 |
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0 |
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1 |
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1 |
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25 |
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1 |
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0 |
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1 |
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50 |
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1 |
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1 |
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3 |
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0 |
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FS1 |
FS0 |
FDRVS |
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FDRV – FDRVS |
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0 |
0 |
89.469kHz |
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20Hz |
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0 |
1 |
89.464kHz |
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25Hz |
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1 |
0 |
89.439kHz |
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50Hz |
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UCC2752
UCC3752
CONNECTION DIAGRAMS
(TOP VIEW) DIL-16, SOIC-16 N or D Packages
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OFFHOOK |
1 |
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16 |
XTAL1 |
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N/C |
2 |
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15 |
XTAL2 |
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GND |
3 |
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14 |
PGND |
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VDD |
4 |
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13 |
DRV2 |
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DCLIM |
5 |
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12 |
DRVS |
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OHD |
6 |
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11 |
DRV1 |
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FS0 |
7 |
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10 |
ENABLE |
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FS1 |
8 |
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9 |
VS12 |
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ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications hold for TA = 0°C to 70°C for the UCC3752 and –40°C to +85°C for the UCC2752, TA = TJ.
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
V12 Supply Current Section |
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Supply Current |
ENABLE = 0V |
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0.5 |
3 |
mA |
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ENABLE = 5V |
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0.5 |
3 |
mA |
Internal Reference with External Bypass Section |
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Output Voltage (VDD) |
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4.85 |
5 |
5.15 |
V |
Load Regulation |
0mA ≤ IVDD ≤ 2mA |
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5 |
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mV |
Line Regulation |
10V < VS12 < 13V, IVDD = 1mA |
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3 |
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mV |
Short Circuit Current |
VDD = 0 |
5 |
10 |
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mA |
Output Drivers Section (DRV1, DRV2) |
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Pull Up Resistance |
ILOAD = 10mA to 20mA |
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6 |
15 |
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Pull Down Resistance |
ILOAD = 10mA to 20mA |
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6 |
15 |
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Rise Time |
CLOAD = 1nF |
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50 |
100 |
nS |
Fall Time |
CLOAD = 1nF |
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50 |
100 |
nS |
Output Drivers Section (DRVS) |
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Pull Up Resistance |
ILOAD = 10mA to 20mA |
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4 |
10 |
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Pull Down Resistance |
ILOAD = 10mA to 20mA |
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4 |
10 |
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Sample Pulse-Width |
Mode 1 (Table 1) |
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280 |
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nS |
Rise Time |
CLOAD = 1nF |
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50 |
100 |
nS |
Fall Time |
CLOAD = 1nF |
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50 |
100 |
nS |
2
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