NSC 5962R8853401VFA, 5962R8853401VEA, 5962R8853401V2A, 5962R8853401FA, 5962R8853401EA Datasheet
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August 1998
54AC109 · 54ACT109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The 'AC/'ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to 'AC/'ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
Features
nICC reduced by 50%
nOutputs source/sink 24 mA
n'ACT109 has TTL-compatible inputs
nStandard Military Drawing (SMD)
Ð'AC109: 5962-89551
Ð'ACT109: 5962-88534
Logic Symbol
IEEE/IEC
DS100267-1
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DS100267-7 |
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Pin Names |
Description |
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J1, J2, |
K |
1, |
K |
2 |
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Data Inputs |
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CP1, CP2 |
Clock Pulse Inputs |
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D2 |
Direct Clear Inputs |
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C |
D1, |
C |
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D2 |
Direct Set Inputs |
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S |
D1, |
S |
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Q1, Q2, |
Q |
1, |
Q |
2 |
Outputs |
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DS100267-2
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
Flop-Flip Triggered-Edge Positive JK Dual 54ACT109 · 54AC109
© 1998 National Semiconductor Corporation |
DS100267 |
www.national.com |
Connection Diagrams
Pin Assignment for DIP and Flatpak
DS100267-3
Truth Table
(each half)
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Inputs |
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Outputs |
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S |
D |
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C |
D |
CP |
J |
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K |
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Q |
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Q |
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L |
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H |
X |
X |
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X |
H |
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L |
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H |
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L |
X |
X |
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X |
L |
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H |
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L |
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L |
X |
X |
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X |
H |
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H |
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H |
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H |
N |
L |
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L |
L |
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H |
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H |
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H |
N |
H |
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L |
Toggle |
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H |
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H |
N |
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L |
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H |
Q0 |
Q0 |
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H |
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H |
N |
H |
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H |
H |
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L |
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H |
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H |
L |
X |
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X |
Q0 |
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Q |
0 |
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H = HIGH Voltage Level
L = LOW Voltage Level
N = LOW-to-HIGH Transition
X = Immaterial
Q0(Q0) = Previous Q0 (Q0) before LOW-to-HIGH Transition of Clock
Logic Diagram (one half shown)
Pin Assignment
for LCC
DS100267-4
DS100267-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com |
2 |
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (VCC) |
−0.5V to +7.0V |
DC Input Diode Current (IIK) |
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VI = −0.5V |
−20 mA |
VI = VCC + 0.5V |
+20 mA |
DC Input Voltage (VI) |
−0.5V to V CC + 0.5V |
DC Output Diode Current (IOK) |
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VO = −0.5V |
−20 mA |
VO = VCC + 0.5V |
+20 mA |
DC Output Voltage (VO) |
−0.5V to V CC + 0.5V |
DC Output Source |
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or Sink Current (IO) |
±50 mA |
DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
±50 mA |
Storage Temperature (TSTG) |
−65ÊC to +150ÊC |
Junction Temperature (TJ) |
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CDIP |
175ÊC |
Recommended Operating
Conditions
Supply Voltage (VCC) |
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'AC |
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2.0V to 6.0V |
'ACT |
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4.5V to 5.5V |
Input Voltage (VI) |
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0V to VCC |
Output Voltage (VO) |
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0V to VCC |
Operating Temperature (TA) |
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54AC/ACT |
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−55ÊC to +125ÊC |
Minimum Input Edge Rate ( |
V/ |
t) |
'AC Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.3V, 4.5V, 5.5V |
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125 mV/ns |
Minimum Input Edge Rate ( |
V/ |
t) |
'ACT Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
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125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT® circuits outside databook specifications.
DC Characteristics for 'AC Family Devices
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54AC |
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Symbol |
Parameter |
VCC |
TA = −55ÊC to +125ÊC |
Units |
Conditions |
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(V) |
Guaranteed Limits |
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VIH |
Minimum High Level |
3.0 |
2.1 |
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VOUT = 0.1V |
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Input Voltage |
4.5 |
3.15 |
V |
or VCC − 0.1V |
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5.5 |
3.85 |
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VIL |
Maximum Low Level |
3.0 |
0.9 |
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VOUT = 0.1V |
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Input Voltage |
4.5 |
1.35 |
V |
or VCC − 0.1V |
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5.5 |
1.65 |
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VOH |
Minimum High Level |
3.0 |
2.9 |
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IOUT = −50 µA |
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Output Voltage |
4.5 |
4.4 |
V |
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5.5 |
5.4 |
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(Note 2) |
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VIN = VIL or VIH |
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3.0 |
2.4 |
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IOH = −12 mA |
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4.5 |
3.7 |
V |
IOH = −24 mA |
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5.5 |
4.7 |
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IOH = −24 mA |
VOL |
Maximum Low Level |
3.0 |
0.1 |
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IOUT = 50 µA |
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Output Voltage |
4.5 |
0.1 |
V |
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5.5 |
0.1 |
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(Note 2) |
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VIN = VIL or VIH |
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3.0 |
0.5 |
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IOL = 12 mA |
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4.5 |
0.5 |
V |
IOL = 24 mA |
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5.5 |
0.5 |
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IOL = 24 mA |
IIN |
Maximum Input |
5.5 |
±1.0 |
µA |
VI = VCC, GND |
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Leakage Current |
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(Note 3) |
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IOLD |
Minimum Dynamic |
5.5 |
50 |
mA |
VOLD = 1.65V Max |
IOHD |
Output Current |
5.5 |
−50 |
mA |
V OHD = 3.85V Min |
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3 |
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